View PIC32MX470F512H_6476923.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2012-2013 microchip technology inc. preliminary ds60001185b-page 1 pic32mx330/350/370/430/450/470 operating conditions ? 2.3v to 3.6v, -40oc to +105oc, dc to 80 mhz core: 80 mhz/105 dmips mips32 ? m4k ? ? mips16e ? mode for up to 40% smaller code size ? code-efficient (c and assembly) architecture ? single-cycle (mac) 32x16 and two-cycle 32x32 multiply clock management ? 0.9% internal oscillator ? programmable plls and oscillator clock sources ? fail-safe clock monitor (fscm) ? independent watchdog timer ? fast wake-up and start-up power management ? low-power management modes (sleep and idle) ? integrated power-on reset, brown-out reset, and high voltage detect ? 0.5 ma/mhz dynamic current (typical) ?40 a i pd current (typical) audio/graphics/touch hmi features ? external graphics interface with up to 34 pmp pins ? audio data communication: i 2 s, lj, rj, usb ? audio data control interface: spi and i 2 c? ? audio data master clock: - generation of fractional clock frequencies - can be synchronized with usb clock - can be tuned in run-time ? charge time measurement unit (ctmu): - supports mtouch? capacitive touch sensing - provides high-resolution time measurement (1 ns) advanced analog features ? adc module: - 10-bit 1 msps rate with one sample and hold (s&h) - up to 28 analog inputs - can operate during sleep mode ? flexible and independent adc trigger sources ? on-chip temperature measurement capability ? comparators: - two dual-input comparator modules - programmable references with 32 voltage points timers/output compare/input capture ? five general purpose timers: - five 16-bit and up to two 32-bit timers/counters ? five output compare (oc) modules ? five input capture (ic) modules ? peripheral pin select (pps) to allow function remap ? real-time clock and calendar (rtcc) module communication interfaces ? usb 2.0-compliant full-speed otg controller ? up to five uart modules (20 mbps): - supports lin 1.2 protocols and irda ? support ? two 4-wire spi modules (25 mbps) ?two i 2 c modules (up to 1 mbaud) with smbus support ? pps to allow function remap ? parallel master port (pmp) direct memory access (dma) ? four channels of hardware dma with automatic data size detection ? 32-bit programmable cyclic redundancy check (crc) ? two additional channels dedicated to usb input/output ? 15 ma or 12 ma source/sink for standard v oh /v ol and up to 22 ma for non-standard v oh 1 ? 5v-tolerant pins ? selectable open drain, pull-ups, and pull-downs ? external interrupts on all i/o pins qualification and class b support ? aec-q100 revg (grade 2 -40oc to +105oc) planned ? class b safety library, iec 60730 debugger development support ? in-circuit and in-application programming ?4-wire mips ? enhanced jtag interface ? unlimited program and six complex data breakpoints ? ieee 1149.2-compatible (jtag) boundary scan packages type qfn tqfp vtla pin count 64 64 100 100 124 i/o pins (up to) 53 53 85 85 85 contact/lead pitch 0.50 0.50 0.40 0.50 0.50 dimensions 9x9x0.9 10x10x1 12x12x1 14x14x1 9x9x0.9 note: all dimensions are in millimeters (mm) unless specified. 32-bit microcontrollers (up to 512 kb flash and 128 kb sram) with audio/graphics/touch (hmi), usb, and advanced analog
pic32mx330/350/370/430/450/470 ds60001185b-page 2 preliminary ? 2012-2013 microchip technology inc. table 1: pic32mx330/350/370/430/450/ 470 controller family features device pins packages program memory (kb) (1) data memory (kb) remappable peripherals 10-bit 1 msps adc (channels) analog comparators usb on-the-go (otg) ctmu i 2 c? pmp rtcc dma channels (programmable/dedicated) i/o pins jtag trace remappable pins timers/capture/compare (2) uart spi/i 2 s external interrupts (3) pic32mx330f064h 64 qfn, tqfp 64+12 16 37 5/5/5 4 2/2 5 28 2 n y 2 y y 4/0 53 y y pic32mx330f064l 100 tqfp 64+12 16 54 5/5/5 5 2/2 5 28 2 n y 2 y y 4/0 85 y y 124 vtla pic32mx350f128h 64 qfn, tqfp 128+12 32 37 5/5/5 4 2/2 5 28 2 n y 2 y y 4/0 53 y y pic32mx350f128l 100 tqfp 128+12 32 54 5/5/5 5 2/2 5 28 2 n y 2 y y 4/0 85 y y 124 vtla pic32mx350f256h 64 qfn, tqfp 256+12 64 37 5/5/5 4 2/2 5 28 2 n y 2 y y 4/0 53 y y pic32mx350f256l 100 tqfp 256+12 64 54 5/5/5 5 2/2 5 28 2 n y 2 y y 4/0 85 y y 124 vtla pic32mx370f512h 64 qfn, tqfp 512+12 128 37 5/5/5 5 2/2 5 28 2 n y 2 y y 4/0 51 y y pic32mx370f512l 100 tqfp 512+12 128 54 5/5/5 5 2/2 5 28 2 n y 2 y y 4/0 83 y y 124 vtla pic32mx430f064h 64 qfn, tqfp 64+12 16 34 5/5/5 4 2/2 5 28 2 y y 2 y y 4/2 51 y y pic32mx430f064l 100 tqfp 64+12 16 51 5/5/5 5 2/2 5 28 2 y y 2 y y 4/2 83 y y 124 vtla pic32mx450f128h 64 qfn, tqfp 128+12 32 34 5/5/5 4 2/2 5 28 2 y y 2 y y 4/2 51 y y pic32mx450f128l 100 tqfp 128+12 32 51 5/5/5 5 2/2 5 28 2 y y 2 y y 4/2 83 y y 124 vtla pic32mx450f256h 64 qfn, tqfp 256+12 64 34 5/5/5 4 2/2 5 28 2 y y 2 y y 4/2 51 y n pic32mx450f256l 100 tqfp 256+12 64 51 5/5/5 5 2/2 5 28 2 y y 2 y y 4/2 83 y y 124 vtla PIC32MX470F512H 64 qfn, tqfp 512+12 128 34 5/5/5 4 2/2 5 28 2 y y 2 y y 4/2 51 y n pic32mx470f512l 100 tqfp 512+12 128 51 5/5/5 5 2/2 5 28 2 y y 2 y y 4/2 83 y y 124 vtla note 1: all devices feature 12 kb of boot flash memory. 2: four out of five timers are remappable. 3: four out of five external interrupts are remappable.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 3 pic32mx330/350/370/430/450/470 pin diagrams 64-pin qfn (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rgx), with the exception of rf6, can be used as a change notification pin (cnax-cngx). see section 12.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. an21/pmd4/re4 trd3/rpe3/ctpls/pmd3/re3 trd2/an20/pmd2/re2 trd1/pmd1/re1 trd0/pmd0/re0 trclk/rpf1/rf1 rpf0/rf0 v dd v cap rd7 rd6 rpd5/pmrd/rd5 rpd4/pmwr/rd4 an26/rpd3/rd3 an25/rpd2/rd2 an24/rpd1/rd1 an22/rpe5/pmd5/re5 sosco/rpc14/t1ck/rc14 an23/pmd6/re6 sosci/rpc13/rc13 an27/pmd7/re7 rpd0/rd0 an16/c1ind/rpg6/sck2/pm a5/rg6 rpd11/pmcs1/rd11 an17/c1inc/rpg7/pma4/rg7 rpd10/pmcs2/rd10 an18/c2ind/rpg8/pma3/rg8 rpd9/rd9 mclr rpd8/rtcc/rd8 an19/c2inc/rpg9/pma2/rg9 pic32mx330f064h v ss v ss osc2/clko/rc15 v dd osc1/clki/rc12 an5/c1ina/rpb5/rb5 v dd an4/c1inb/rb4 scl1/rg2 pged3/an3/c2ina/rpb3/rb3 sda1/rg3 pgec3/an2/c2inb/r pb2/cted13/rb2 rpf 6/sck1/int0/rf6 pgec1/vref-/cvref-/a n1/rpb1/cted12/rb1 rpf2/rf2 pged1/v ref +/cv ref +/an0/rpb0/pma6/rb0 rpf3/rf3 pgec2/an6/rpb6/rb6 pged2/an7/rpb7/cted3/rb7 av dd avss an8/rpb8/cted10/rb8 an9/rpb9/cted4/pma7/rb9 tms/cv refout /an10/rpb10/cted11/pma13/rb10 tdo/an11/pma12/rb11 v ss v dd tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/rpb14/cted 5/pma1/rb14 an15/rpb15/ocfb/cted6/pma0/rb15 sda2/rpf4/pma9/rf4 scl2/rpf5/pma8/rf5 64 63 62 61 60 59 58 57 56 55 22 23 24 25 26 27 28 29 30 31 3 40 39 38 37 36 35 34 33 4 5 7 8 9 10 11 1 2 42 41 6 32 43 54 14 15 16 12 13 17 18 19 20 21 45 44 47 46 48 53 52 51 50 49 pic32mx350f128h pic32mx350f256h pic32mx370f512h
pic32mx330/350/370/430/450/470 ds60001185b-page 4 preliminary ? 2012-2013 microchip technology inc. pin diagrams (continued) 64-pin qfn (1,2,3) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rgx), with the exception of rf6, can be used as a change notification pin (cnax-cngx). see section 12.0 ?i/o ports? for more information. 3: the metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to v ss externally. an21/pmd4/re4 trd3/rpe3/ctpls/pmd3/re3 trd2/an20/pmd2/re2 trd1/pmd1/re1 trd0/pmd0/re0 trclk/rpf1/rf1 rpf0/rf0 v dd v cap rd7 rd6 rpd5/pmrd/rd5 rpd4/pmwr/rd4 an26/rpd3/rd3 an25/rpd2/sck1/rd2 an24/rpd1/rd1 an22/rpe5/pmd5/re5 sosco/rpc14/t1ck/rc14 an23/pmd6/re6 sosci/rpc13/rc13 an27/pmd7/re7 rpd0/int0/rd0 an16/c1ind/rpg6/sck2/pma5/rg6 rpd11/pmcs1/rd11 an17/c1inc/rpg7/pma4/rg7 scl1/rpd10/pmcs2/rd10 an18/c2ind/rpg8/pma3/rg8 sda1/rpd9/rd9 mclr rpd8/rtcc/rd8 an19/c2inc/rpg9/pma2/rg9 pic32mx430f064h v ss v ss osc2/clko/rc15 v dd osc1/clki/rc12 an5/c1ina/rpb5/v buson /rb5 v dd an4/c1inb/rb4 d+ pged3/an3/c2ina/rpb3/rb3 d- pgec3/an2/c2inb/ rpb2/cted13/rb2 v usb 3 v 3 pgec1/v ref -/cv ref -/an1/rpb1/cted12/rb1 v bus pged1/v ref +/cv ref +/an0/rpb0/pma6/rb0 usbid/rf3 pgec2/an6/rpb6/rb6 pged2/an7/rpb7/cted3/rb7 av dd av ss an8/rpb8/cted10/rb8 an9/rpb9/cted4/pma7/rb9 tms/cv refout /an10/rpb10/ct ed11/pma13/rb10 tdo/an11/pm a12/rb11 v ss v dd tck/an12/pm a11/rb12 tdi/an13/pma10/rb13 an14/rpb14/cted 5/pma1/rb14 an15/rpb15/ocfb/c ted6/pma0/rb15 sda2/rpf4/pma9/rf4 scl2/rpf5/pma8/rf5 64 63 62 61 60 59 58 57 56 55 22 23 24 25 26 27 28 29 30 31 3 40 39 38 37 36 35 34 33 4 5 7 8 9 10 11 1 2 42 41 6 32 43 54 14 15 16 12 13 17 18 19 20 21 45 44 47 46 48 53 52 51 50 49 pic32mx450f128h pic32mx450f256h PIC32MX470F512H
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 5 pic32mx330/350/370/430/450/470 pin diagrams (continued) 64-pin tqfp (1,2) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rgx), with the exception of rf6, can be used as a change notification pin (cnax-cngx). see section 12.0 ?i/o ports? for more information. an21/pmd4/re4 trd3/rpe3/ctpls/pmd3/re3 trd2/an20/pmd2/re2 trd1/pmd1/re1 trd0/pmd0/re0 trclk/rpf1/rf1 rpf0/rf0 v dd v cap rd7 rd6 rpd5/pmrd/rd5 rpd4/pmwr/rd4 an26/rpd3/rd3 an25/rpd2/rd2 an24/rpd1/rd1 an22/rpe5/p md5/re5 sosco/rpc14/t1ck/rc14 an23/pmd6/re6 sosci/rpc13/rc13 an27/pmd7/re7 rpd0/rd0 an16/c1ind/rpg6/sck2/pma5/rg6 rpd11/pmcs1/rd11 an17/c1inc/rpg7/pma4/rg7 rpd10/pmcs2/rd10 an18/c2ind/rpg8/pma3/rg8 rpd9/rd9 mclr rpd8/rtcc/rd8 an19/c2inc/rpg9/pma2/rg9 pic32mx330f064h v ss v ss osc2/clko/rc15 v dd osc1/clki/rc12 an5/c1ina/rpb5/rb5 v dd an4/c1inb/rb4 scl1/rg2 pged3/an3/c2ina/ rpb3/rb3 sda1/rg3 pgec3/an2/c2inb/rpb2/cte d13/rb2 rpf6/sck1/int0/rf6 pgec1/v ref -/cv ref -/an1/rpb1/cted12/rb1 rpf2/rf2 pged1/v ref +/cv ref +/an0/rpb0/pma6/rb0 rpf3/rf3 pgec2/an6/rpb6/rb6 pged2/an7/r pb7/cted3//rb7 av dd av ss an8/rpb8/cted10//rb8 an9/rpb9/cted4/pma7/rb9 tms/cv refout /an10/rpb10/cted 11//pma13/rb10 tdo/an11/pma12/rb11 v ss v dd tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/rpb14/cted 5/pma1/rb14 an15/rpb15/ocfb/cted6/pma0/rb15 sda2/rpf4/pma9/rf4 scl2/rpf5/pma8/rf5 64 63 62 61 60 59 58 57 56 55 22 23 24 25 26 27 28 29 30 31 3 40 39 38 37 36 35 34 33 4 5 7 8 9 10 11 1 2 42 41 6 32 43 54 14 15 16 12 13 17 18 19 20 21 45 44 47 46 48 53 52 51 50 49 pic32mx350f128h pic32mx350f256h pic32mx370f512h
pic32mx330/350/370/430/450/470 ds60001185b-page 6 preliminary ? 2012-2013 microchip technology inc. pin diagrams (continued) 64-pin tqfp (1,2) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rgx), with the exception of rf6, can be used as a change notification pin (cnax-cngx). see section 12.0 ?i/o ports? for more information. an21/pmd4/re4 trd3/rpe3/ctpls/pmd3/re3 trd2/an20/pmd2/re2 trd1/pmd1/re1 trd0/pmd0/re0 trclk/rpf1/rf1 rpf0/rf0 v dd v cap rd7 rd6 rpd5/pmrd/rd5 rpd4/pmwr/rd4 an26/rpd3/rd3 an25/rpd2/sck1/rd2 an24/rpd1/rd1 an22/rpe5/pmd5/re5 sosco/rpc14/t1ck/rc14 an23/pmd6/re6 sosci/rpc13/rc13 an27/pmd7/re7 rpd0/int0/rd0 an16/c1ind/rpg6/sck2/p ma5/rg6 rpd11/pmcs1/rd11 an17/c1inc/rpg7/pma4/rg7 scl1/rpd10/pmcs2/rd10 an18/c2ind/rpg8/pma3/rg8 sda1/rpd9/rd9 mclr rpd8/rtcc/rd8 an19/c2inc/rpg9/pma2/rg9 pic32mx430f064h v ss v ss osc2/clko/rc15 v dd osc1/clki/rc12 an5/c1ina/rpb5/v buson /rb5 v dd an4/c1inb/rb4 d+ pged3/an3/c2ina/rpb3/rb3 d- pgec3/an2/c2inb/ rpb2/cted13/rb2 v usb 3 v 3 pgec1/v ref -/cv ref -/an1/rpb1/cted12/rb1 v bus pged1/v ref +/cv ref +/an0/rpb0/pma6/rb0 usbid/rf3 pgec2/an6/rpb6/rb6 pged2/an7/rpb7 /cted3//rb7 av dd av ss an8/rpb8/cted10//rb8 an9/rpb9/cted4/pma7/rb9 tms/cv refout /an10/rpb10/ct ed11//pma13/rb10 tdo/an11/pma12/rb11 v ss v dd tck/an12/pma11/rb12 tdi/an13/pma10/rb13 an14/rpb14/cted 5/pma1/rb14 an15/rpb15/ocfb/cted6/pma0/rb15 sda2/rpf4/pma9/rf4 scl2/rpf5/pma8/rf5 64 63 62 61 60 59 58 57 56 55 22 23 24 25 26 27 28 29 30 31 3 40 39 38 37 36 35 34 33 4 5 7 8 9 10 11 1 2 42 41 6 32 43 54 14 15 16 12 13 17 18 19 20 21 45 44 47 46 48 53 52 51 50 49 pic32mx450f128h pic32mx450f256h PIC32MX470F512H
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 7 pic32mx330/350/370/430/450/470 pin diagrams (continued) 100-pin tqfp (1,2) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rgx), with the exception of rf6, can be used as a change notification pin (cnax-cngx). see section 12.0 ?i/o ports? for more information. an21/pmd4/re4 rpe3/ctpls/pmd3/re3 an20/pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 trd3/cted8/ra7 trclk/ra6 rpg0/pmd8/rg0 rpg1/pmd9/rg1 rpf1/pmd10/rf1 rpf0/pmd11/rf0 v dd v cap pmd15/rd7 pmd14/rd6 rpd5/pmrd/rd5 rpd4/pmwr/rd4 pmd13/rd13 rpd12/pmd12/rd12 an26/rpd3/rd3 an25/rpd2/rd2 an24/rpd1/rd1 rg15 v ss v dd sosco/rpc14/t1ck/rc14 an22/rpe5/pmd5/re5 sosci/rpc13/rc13 an23/pmd6/re6 rpd0/rd0 an27/pmd7/re7 rpd11/pmcs1/rd11 rpc1/rc1 rpd10/pmcs2/rd10 rpc2/rc2 rpd9/rd9 rpc3/rc3 rpd8/rtcc/rd8 rpc4/cted7/rc4 rpa15/ra15 an16/c1ind/rpg6/sck2/pma5/rg6 rpa14/ra14 an17/c1inc/rpg7/pma4/rg7 v ss an18/c2ind/rpg8/pma3/rg8 osc2/clko/rc15 mclr osc1/clki/rc12 an19/c2inc/rpg9/pma2/rg9 v dd v ss tdo/ra5 v dd tdi/cted9/ra4 tms/cted1/ra0 sda2/ra3 rpe8/re8 scl2/ra2 rpe9/re9 scl1/rg2 an5/c1ina/rpb5/rb5 sda1/rg3 an4/c1inb/rb4 rpf6/sck1/int0/rf6 pged3/an3/c2ina/rpb3/rb3 rpf7/rf7 rpf8/rf8 pgec1/an1/rpb1/cted12/rb1 rpf2/rf2 pged1/an0/rpb0/rb0 rpf3/rf3 pgec2/an6/rpb6/rb6 pged2/an7/rpb7/cted3/rb7 vref-/cvref-/pma7/ra9 vref+/cvref+/pma6/ra10 av dd av ss an8/rpb8/cted10/rb8 an9/rpb9/cted4/rb9 cv refout /an10/rpb10/cted11pma13/rb10 an11/pma12//rb11 tck/cted2/ra1 rpf13/rf13 rpf12/rf12 an12/pma11/rb12 an13/pma10/rb13 an14/rpb14/cted5/pma1/rb14 an15/rpb15/ocfb/cted6/pma0/rb15 rpd14/rd14 rpd15/rd15 rpf4/pma9/rf4 rpf5/pma8/rf5 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 56 17 18 19 21 22 1 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 55 54 53 52 51 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 95 76 77 96 98 97 99 100 pic32mx330f064l pic32mx350f128l pgec3/an2/c2inb/rpb2/cted13/rb2 v ss v dd v ss v dd pic32mx350f256l 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 27 46 47 48 49 50 26 pic32mx370f512l
pic32mx330/350/370/430/450/470 ds60001185b-page 8 preliminary ? 2012-2013 microchip technology inc. pin diagrams (continued) 100-pin tqfp (1,2) = pins are up to 5v tolerant note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rgx), with the exception of rf6, can be used as a change notificat ion pin (cnax-cncx). see section 12.0 ?i/o ports? for more information. an21/pmd4/re4 rpe3/pmd3/re3 an20/ctpls/pmd2/re2 trd0/rg13 trd1/rg12 trd2/rg14 pmd1/re1 pmd0/re0 trd3/cted8/ra7 trclk/ra6 rpg0/pmd8/rg0 rpg1/pmd9/rg1 rpf1/pmd10/rf1 rpf0/pmd11/rf0 v dd v cap pmd15/rd7 pmd14/rd6 rpd5/pmrd/rd5 rpd4/pmwr/rd4 pmd13/rd13 rpd12/pmd12/rd12 an26/rpd3/rd3 an25/rpd2/rd2 an24/rpd1/rd1 rg15 vss v dd sosco/rpc14/t1ck/rc14 an22/rpe5/pmd5/re5 sosci/rpc13/rc13 an23/pmd6/re6 rpd0/int0/rd0 an27/pmd7/re7 rpd11/pmcs1/rd11 rpc1/rc1 rpd10/sck1/pmcs2/rd10 rpc2/rc2 rpd9/rd9 rpc3/rc3 rpd8/rtcc/rd8 rpc4/cted7/rc4 sda1/rpa15/ra15 an16/c1ind/rpg6/sck2/pma5/rg6 scl1/rpa14/ra14 an17/c1inc/rpg7/pma4/rg7 v ss an18/c2ind/rpg8/pma3/rg8 osc2/clko/rc15 mclr osc1/clki/rc12 an19/c2inc/rpg9/pma2/rg9 v dd v ss tdo/ra5 v dd tdi/cted9/ra4 tms/cted1/ra0 sda2/ra3 scl2/ra2 rpe9/re9 d+ an5/c1ina/rpb5/v buson /rb5 d- an4/c1inb/rb4 v usb 3 v 3 pged3/an3/c2ina/rpb3/rb3 v bus pgec3/an2/c2inb/rpb2/cted13/rb2 rpf8/rf8 pgec1/an1/rpb1/cted12/rb1 rpf2/rf2 pged1/an0/rpb0/rb0 usbid/rf3 pgec2/an6/rpb6/rb6 pged2/an7/rpb7/cted3/rb7 v ref -/cvref-/pma7/ra9 v ref +/cv ref +/pma6/ra10 av dd av ss an8/rpb8/cted10/rb8 an9/rpb9/cted4/rb9 cv refout /an10/rpb10/cted11/pma13/rb10 an11/pma12/rb11 v ss v dd tck/cted2/ra1 rpf13/rf13 rpf12/rf12 an12/pma11/rb12 an13/pma10/rb13 an14/rpb14/cted5/pma1/rb14 an15/rpb15/ocfb/cted6/pma0/rb15 v ss v dd rpd14/rd14 rpd15/rd15 rpf4/pma9/rf4 rpf5/pma8/rf5 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 1 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 27 46 47 48 49 55 54 53 52 51 50 26 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 95 76 77 96 98 97 99 100 pic32mx430f064l pic32mx450f128l rpe8/re8 pic32mx450f256l pic32mx470f512l
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 9 pic32mx330/350/370/430/450/470 pin diagrams (continued) 124-pin vtla (1) = pins are up to 5v tolerant note 1: see ta b l e 2 for the full list of pin names. a68 a67 a66 a65 a64 a63 a62 a61 a60 a59 a58 a57 a56 a55 a54 a53 a52 a51 a1 b56 b55 b54 b53 b52 b51 b50 b49 b48 b47 b46 b45 b44 b43 b42 a50 a2 b1 a49 a16 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 a35 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 a32 a33 a34 a3 b2 b41 a48 a4 b3 b40 a47 a5 b4 b39 a46 a6 b5 b38 a45 a7 b6 b37 a44 a8 b7 b36 a43 a10 b9 b34 a41 a11 b10 b33 a40 a12 b11 b32 a39 a13 b12 b31 a38 a14 b13 b30 a37 a15 b29 a36 a9 b8 b35 a42 pic32mx330f064l pic32mx350f128l b32 b31 b30 pic32mx350f256l pic32mx370f512l
pic32mx330/350/370/430/450/470 ds60001185b-page 10 preliminary ? 2012-2013 microchip technology inc. table 2: pin names: pic32mx3xxl devices (1,2) package bump # full pin name package bump # full pin name a1 no connect a52 an24/rpd1/rd1 a2 rg15 a53 an26/rpd3/rd3 a3 v ss a54 pmd13/rd13 a4 an23/pmd6/re6 a55 rpd5/pmrd/rd5 a5 rpc1/rc1 a56 pmd15/rd7 a6 rpc3/rc3 a57 no connect a7 an16/c1ind/rpg6/sck2/pma5/rg6 a58 no connect a8 an18/c2ind/rpg8/pma 3/rg8 a59 no connect a9 an19/c2inc/rpg9/pma2/ rg9 a60 rpf1/pmd10/rf1 a10 v dd a61 rpg0/pmd8/rg0 a11 rpe8/re8 a62 trd3/cted8/ra7 a12 an5/c1ina/rpb5/rb5 a63 v ss a13 pged3/an3/c2ina/rpb3/rb3 a64 pmd1/re1 a14 v dd a65 trd1/rg12 a15 pgec1/an1/rpb1/cted12/rb1 a66 an20/pmd2/re2 a16 no connect a67 an21/pmd4/re4 a17 no connect a68 no connect a18 no connect b1 v dd a19 no connect b2 an22/rpe5/pmd5/re5 a20 pgec2/an6/rpb6/rb6 b3 an27/pmd7/re7 a21 v ref -/cv ref -/pma7/ra9 b4 rpc2/rc2 a22 av dd b5 rpc4/cted7/rc4 a23 an8/rpb8/cted10/rb8 b6 a n17/c1inc/rpg7/pma4/rg7 a24 cv refout /an10/rpb10/cted11/pma13/rb10 b7 mclr a25 v ss b8 v ss a26 tck/cted2/ra1 b9 tms/cted1/ra0 a27 rpf12/rf12 b10 rpe9/re9 a28 an13/pma10/rb13 b11 an4/c1inb/rb4 a29 an15/rpb15/ocfb/cted6/pma0/rb15 b12 v ss a30 v dd b13 pgec3/an2/c2inb/rpb2/cted13/rb2 a31 rpd15/rd15 b14 pged1/an0/rpb0/rb0 a32 rpf5/pma8/rf5 b15 no connect a33 no connect b16 pged2/an7/rpb7/cted3/rb7 a34 no connect b17 v ref +/cv ref +/pma6/ra10 a35 rpf3/rf3 b18 av ss a36 rpf2/rf2 b19 an9/rpb9/cted4/rb9 a37 rpf7/rf7 b20 an11/pma12/rb11 a38 sda1/rg3 b21 v dd a39 scl2/ra2 b22 rpf13/rf13 a40 tdi/cted9/ra4 b23 an12/pma11/rb12 a41 v dd b24 an14/rpb14/cted5/pma1/rb14 a42 osc2/clko/rc15 b25 v ss a43 v ss b26 rpd14/rd14 a44 rpa15/ra15 b27 rpf4/pma9/rf4 a45 rpd9/rd9 b28 no connect a46 rpd11/pmcs1/rd11 b29 rpf8/rf8 a47 sosci/rpc13/rc13 b30 rpf6/scki/int0/rf6 a48 v dd b31 scl1/rg2 a49 no connect b32 sda2/ra3 a50 no connect b33 tdo/ra5 a51 no connect b34 osc1/clki/rc12 note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rgx), with the exception of rf6, can be used as a change notification pin (cnax-cngx). see section 12.0 ?i/o ports? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 11 pic32mx330/350/370/430/450/470 b35 no connect b46 v cap b36 rpa14/ra14 b47 no connect b37 rpd8/rtcc/rd8 b48 v dd b38 rpd10/pmcs2/rd10 b49 rpf0/pmd11/rf0 b39 rpd0/rd0 b50 rpg1/pmd9/rg1 b40 sosco/rpc14/t1ck/rc14 b51 trclk/ra6 b41 v ss b52 pmd0/re0 b42 an25/rpd2/rd2 b53 v dd b43 rpd12/pmd12/rd12 b54 trd2/rg14 b44 rpd4/pmwr/rd4 b55 trd0/rg13 b45 pmd14/rd6 b56 rpe3/ctpls/pmd3/re3 table 2: pin names: pic32mx3xxl devices (1,2) (continued) package bump # full pin name package bump # full pin name note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rgx), with the exception of rf6, can be used as a change notification pin (cnax-cngx). see section 12.0 ?i/o ports? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 12 preliminary ? 2012-2013 microchip technology inc. pin diagrams (continued) 124-pin vtla (1) = pins are up to 5v tolerant pic32mx430f064l pic32mx450f128l a68 a67 a66 a65 a64 a63 a62 a61 a60 a59 a58 a57 a56 a55 a54 a53 a52 a51 a1 b56 b55 b54 b53 b52 b51 b50 b49 b48 b47 b46 b45 b44 b43 b42 a50 a2 b1 a49 a16 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 a35 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 a32 a33 a34 a3 b2 b41 a48 a4 b3 b40 a47 a5 b4 b39 a46 a6 b5 b38 a45 a7 b6 b37 a44 a8 b7 b36 a43 a10 b9 b34 a41 a11 b10 b33 a40 a12 b11 b32 a39 a13 b12 b31 a38 a14 b13 b30 a37 a15 b29 a36 a9 b8 b35 a42 note 1: see table 3 for the full list of pin names. pic32mx450f256l pic32mx470f512l
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 13 pic32mx330/350/370/430/450/470 table 3: pin names: pic32mx4xxl devices (1,2) package bump # full pin name package bump # full pin name a1 no connect a52 an24/rpd1/rd1 a2 rg15 a53 an26/rpd3/rd3 a3 v ss a54 pmd13/rd13 a4 an23/pmd6/re6 a55 rpd5/pmrd/rd5 a5 rpc1/rc1 a56 pmd15/rd7 a6 rpc3/rc3 a57 no connect a7 an16/c1ind/rpg6/sck2/pma5/rg6 a58 no connect a8 an18/c2ind/rpg8/pma 3/rg8 a59 no connect a9 an19/c2inc/rpg9/pma2/rg9 a60 rpf1/pmd10/rf1 a10 v dd a61 rpg0/pmd8/rg0 a11 rpe8/re8 a62 trd3/cted8/ra7 a12 an5/c1ina/rpb5/v buson /rb5 a63 v ss a13 pged3/an3/c2ina/rpb3/rb3 a64 pmd1/re1 a14 v dd a65 trd1/rg12 a15 pgec1/an1/rpb1/cted12/rb1 a66 an20/pmd2/re2 a16 no connect a67 an21/pmd4/re4 a17 no connect a68 no connect a18 no connect b1 v dd a19 no connect b2 an22/rpe5/pmd5/re5 a20 pgec2/an6/rpb6/rb6 b3 an27/pmd7/re7 a21 v ref -/cv ref -/pma7/ra9 b4 rpc2/rc2 a22 av dd b5 rpc4/cted7/rc4 a23 an8/rpb8/cted10/rb8 b6 a n17/c1inc/rpg7/pma4/rg7 a24 cv refout /an10/rpb10/cted11/pma13/rb10 b7 mclr a25 v ss b8 v ss a26 tck/cted2/ra1 b9 tms/cted1/ra0 a27 rpf12/rf12 b10 rpe9/re9 a28 an13/pma10/rb13 b11 an4/c1inb/rb4 a29 an15/rpb15/ocfb/cted6/pma0/rb15 b12 v ss a30 v dd b13 pgec3/an2/c2inb/rpb2/cted13/rb2 a31 rpd15/rd15 b14 pged1/an0/rpb0/rb0 a32 rpf5/pma8/rf5 b15 no connect a33 no connect b16 pged2/an7/rpb7/cted3/rb7 a34 no connect b17 v ref +/cv ref +/pma6/ra10 a35 usbid/rf3 b18 av ss a36 rpf2/rf2 b19 an9/rpb9/cted4/rb9 a37 v bus b20 an11/pma12/rb11 a38 d- b21 v dd a39 scl2/ra2 b22 rpf13/rf13 a40 tdi/cted9/ra4 b23 an12/pma11/rb12 a41 v dd b24 an14/rpb14/cted5/pma1/rb14 a42 osc2/clko/rc15 b25 v ss a43 v ss b26 rpd14/rd14 a44 sda1/rpa15/ra15 b27 rpf4/pma9/rf4 a45 rpd9/rd9 b28 no connect a46 rpd11/pmcs1/rd11 b29 rpf8/rf8 a47 sosci/rpc13/rc13 b30 v usb 3 v 3 a48 v dd b31 d+ a49 no connect b32 sda2/ra3 a50 no connect b33 tdo/ra5 a51 no connect b34 osc1/clki/rc12 note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rgx), with the exception of rf6, can be used as a change notification pin (cnax-cngx). see section 12.0 ?i/o ports? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 14 preliminary ? 2012-2013 microchip technology inc. b35 no connect b46 v cap b36 scl1/rpa14/ra14 b47 no connect b37 rpd8/rtcc/rd8 b48 v dd b38 rpd10/sck1/pmcs2/rd10 b49 rpf0/pmd11/rf0 b39 rpd0/int0/rd0 b50 rpg1/pmd9/rg1 b40 sosco/rpc14/t1ck/rc14 b51 trclk/ra6 b41 v ss b52 pmd0/re0 b42 an25/rpd2/rd2 b53 v dd b43 rpd12/pmd12/rd12 b54 trd2/rg14 b44 rpd4/pmwr/rd4 b55 trd0/rg13 b45 pmd14/rd6 b56 rpe3/ctpls/pmd3/re3 table 3: pin names: pic32mx4xxl devices (1,2) (continued) package bump # full pin name package bump # full pin name note 1: the rpn pins can be used by remappable peripherals. see table 1 for the available peripherals and section 12.3 ?peripheral pin select? for restrictions. 2: every i/o port pin (rax-rgx), with the exception of rf6, can be used as a change notification pin (cnax-cngx). see section 12.0 ?i/o ports? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 15 pic32mx330/350/370/430/450/470 table of contents 1.0 device overview ............................................................................................................. ........................................................... 17 2.0 guidelines for getting started with 32-bit mcus............................................................................. ........................................... 27 3.0 cpu......................................................................................................................... ................................................................... 33 4.0 memory organization ......................................................................................................... ........................................................ 37 5.0 flash program memory........................................................................................................ ...................................................... 93 6.0 resets ...................................................................................................................... .................................................................. 97 7.0 interrupt controller ........................................................................................................ ........................................................... 101 8.0 oscillator configuration .................................................................................................... ........................................................ 109 9.0 prefetch cache.............................................................................................................. ........................................................... 119 10.0 direct memory access (dma) controller ...................................................................................... ........................................... 129 11.0 usb on-the-go (otg)........................................................................................................ .................................................... 145 12.0 i/o ports .................................................................................................................. ................................................................. 167 13.0 timer1 ..................................................................................................................... ................................................................. 177 14.0 timer2/3, timer4/5 ......................................................................................................... .......................................................... 181 15.0 input capture.............................................................................................................. .............................................................. 185 16.0 output compare............................................................................................................. .......................................................... 189 17.0 serial peripheral interface (spi).......................................................................................... ..................................................... 191 18.0 inter-integrated circuit? (i 2 c?)............................................................................................................................ .................. 199 19.0 universal asynchronous receiv er transmitter (uart) ......................................................................... .................................. 205 20.0 parallel master port (pmp)................................................................................................. ...................................................... 211 21.0 real-time clock and calendar (rtcc)........................................................................................ ........................................... 219 22.0 10-bit analog-to-digital converter (adc) ................................................................................... .............................................. 229 23.0 comparator ................................................................................................................. ............................................................. 237 24.0 comparator voltage reference (c v ref ) .............................................................................................................................. ... 241 25.0 charge time measurement unit (ctmu) ....................................................................................... ........................................ 243 26.0 power-saving features ..................................................................................................... ...................................................... 247 27.0 special features ........................................................................................................... ........................................................... 251 28.0 instruction set ............................................................................................................ .............................................................. 263 29.0 development support........................................................................................................ ....................................................... 265 30.0 electrical characteristics ................................................................................................. ......................................................... 269 31.0 dc and ac device characteristics graphs.................................................................................... .......................................... 315 32.0 packaging information...................................................................................................... ........................................................ 319 the microchip web site ......................................................................................................... ............................................................ 339 customer change notification service ........................................................................................... ................................................... 339 customer support ............................................................................................................... ............................................................... 339 reader response ................................................................................................................ .............................................................. 340 product identification system .................................................................................................. .......................................................... 341 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publicat ions to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact t he marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the ve rsion number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documen tation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a partic ular device, please check with one of the following: ? microchip?s worldwide web site: http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and dat a sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
pic32mx330/350/370/430/450/470 ds60001185b-page 16 preliminary ? 2012-2013 microchip technology inc. referenced sources this device data sheet is based on the following individual sections of the ?pic32 family reference manual? . these documents should be considered as the general reference for the operation of a particular module or device feature. ? section 1. ?introduction? (ds60001127) ? section 2. ?cpu? (ds60001113) ? section 3. ?memory organization? (ds60001115) ? section 4. ?prefetch cache? (ds60001119) ? section 5. ?flash program memory? (ds60001121) ? section 6. ?oscillator configuration? (ds60001112) ? section 7. ?resets? (ds60001118) ? section 8. ?interrupt controller? (ds60001108) ? section 9. ?watchdog timer and power-up timer? (ds60001114) ? section 10. ?power-saving features? (ds60001130) ? section 12. ?i/o ports? (ds60001120) ? section 13. ?parallel master port (pmp)? (ds60001128) ? section 14. ?timers? (ds60001105) ? section 15. ?input capture? (ds60001122) ? section 16. ?output compare? (ds60001111) ? section 17. ?10-bit analog-to -digital converter (adc)? (ds60001104) ? section 19. ?comparator? (ds60001110) ? section 20. ?comparator voltage reference (cv ref )? (ds60001109) ? section 21. ?universal asynchronous receiver transmitter (uart)? (ds60001107) ? section 23. ?serial peri pheral interface (spi)? (ds60001106) ? section 24. ?inter-integrated circuit? (i 2 c?)? (ds60001116) ? section 27. ?usb on-the-go (otg)? (ds60001126) ? section 29. ?real-time clock and calendar (rtcc)? (ds60001125) ? section 31. ?direct memory access (dma) controller? (ds60001117) ? section 32. ?configuration? (ds60001124) ? section 33. ?programming and diagnostics? (ds60001129) ? section 37. ?charge time measurement unit (ctmu)? (ds60001167) note: to access the documents listed below, browse to the documentation section of the microchip web site ( www.microchip.com ).
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 17 pic32mx330/350/370/430/450/470 1.0 device overview this document contains devic e-specific information for pic32mx330/350/370/430/450/470 devices. figure 1-1 illustrates a general block diagram of the core and peripheral modules in the pic32mx330/350/ 370/430/450/470 family of devices. table 1-1 lists the functions of the various pins shown in the pinout diagrams. figure 1-1: pic32mx330/350/370/430/450/470 block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. note: not all features are availa ble on all devices. refer to table 1: ?pic32mx330/350/370/430/450/470 controller family features? for the list of features by device. uart1-5 comparators porta/cna portd/cnd porte/cne portf/cnf portg/cng portb/cnb jtag priority dmac icd mips32 ? m4k ? cpu core is ds ejtag int bus matrix cache & prefetch data ram peripheral bridge 128 128-bit wide flash 32 32 32 32 32 peripheral bus clocked by pbclk program flash memory controller 32 module 32 32 interrupt controller bscan portc/cnc pmp i2c1,2 spi1,2 ic1-5 pwm oc1-5 osc1/clki osc2/clko v dd , timing generation v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset precision reference band gap frc/lprc oscillators regulator voltage v cap osc/s osc oscillators pll dividers sysclk pbclk peripheral bus clocked by sysclk usb pll-usb usbclk 32 rtcc 10-bit adc timer1-5 32 32 remappable pins ctmu 1-2
pic32mx330/350/370/430/450/470 ds60001185b-page 18 preliminary ? 2012-2013 microchip technology inc. table 1-1: pinout i/o descriptions pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla an0 16 25 b14 i analog analog input channels. an1 15 24 a15 i analog an2 14 23 b13 i analog an3 13 22 a13 i analog an4 12 21 b11 i analog an5 11 20 a12 i analog an6 17 26 a20 i analog an7 18 27 b16 i analog an8 21 32 a23 i analog an9 22 33 b19 i analog an10 23 34 a24 i analog an11 24 35 b20 i analog an12 27 41 b23 i analog an13 28 42 a28 i analog an14 29 43 b24 i analog an15 30 44 a29 i analog an16 4 10 a7 i analog an17 5 11 b6 i analog an18 6 12 a8 i analog an19 8 14 a9 i analog an20 62 98 a66 i analog an21 64 100 a67 i analog an22 1 3 b2 i analog an23 2 4 a4 i analog an24 49 76 a52 i analog an25 50 77 b42 i analog an26 51 78 a53 i analog an27 3 5 b3 i analog clki 39 63 b34 i st/cmos external clock source input. always associated with osc1 pin function. clko 40 64 a42 o ? oscillator crystal output. connects to crystal or reso- nator in crystal oscillator mode. optionally functions as clko in rc and ec modes. always associated with the osc2 pin function. osc1 39 63 b34 i st/cmos oscillator crystal input. st buffer when configured in rc mode; cmos otherwise. osc2 40 64 a42 i/o ? oscillator crystal output. connects to crystal or reso- nator in crystal oscillator mode. optionally functions as clko in rc and ec modes. sosci 47 73 a47 i st/cmos 32.768 khz low-power oscillator crystal input; cmos otherwise. sosco 48 74 b40 o ? 32.768 khz low-power oscillator crystal output. legend: cmos = cmos compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = ttl input buffer note 1: this pin is available on pic32mx3xx devices only. 2: this pin is available on pic32mx4xx devices only.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 19 pic32mx330/350/370/430/450/470 ic1 pps pps pps i st capture input 1-5 ic2 pps pps pps i st ic3 pps pps pps i st ic4 pps pps pps i st ic5 pps pps pps i st oc1 pps pps pps o st output compare output 1 oc2 pps pps pps o st output compare output 2 oc3 pps pps pps o st output compare output 3 oc4 pps pps pps o st output compare output 4 oc5 pps pps pps o st output compare output 5 ocfa pps pps pps i st output compare fault a input ocfb 30 44 a29 i st output compare fault b input int0 35 (1) , 46 (2) 55 (1) , 72 (2) b30 (1) , b39 (2) i st external interrupt 0 int1 pps pps pps i st external interrupt 1 int2 pps pps pps i st external interrupt 2 int3 pps pps pps i st external interrupt 3 int4 pps pps pps i st external interrupt 4 ra0 ? 17 b9 i/o st porta is a bidirectional i/o port ra1 ? 38 a26 i/o st ra2 ? 58 a39 i/o st ra3 ? 59 b32 i/o st ra4 ? 60 a40 i/o st ra5 ? 61 b33 i/o st ra6 ? 91 b51 i/o st ra7 ? 92 a62 i/o st ra9 ? 28 a21 i/o st ra10 ? 29 b17 i/o st ra14 ? 66 b36 i/o st ra15 ? 67 a44 i/o st table 1-1: pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = ttl input buffer note 1: this pin is available on pic32mx3xx devices only. 2: this pin is available on pic32mx4xx devices only.
pic32mx330/350/370/430/450/470 ds60001185b-page 20 preliminary ? 2012-2013 microchip technology inc. rb0 16 25 b14 i/o st portb is a bidirectional i/o port rb1 15 24 a15 i/o st rb2 14 23 b13 i/o st rb3 13 22 a13 i/o st rb4 12 21 b11 i/o st rb5 11 20 a12 i/o st rb6 17 26 a20 i/o st rb7 18 27 b16 i/o st rb8 21 32 a23 i/o st rb9 22 33 b19 i/o st rb10 23 34 a24 i/o st rb11 24 35 b20 i/o st rb12 27 41 b23 i/o st rb13 28 42 a28 i/o st rb14 29 43 b24 i/o st rb15 30 44 a29 i/o st rc1 ? 6 a5 i/o st portc is a bidirectional i/o port rc2 ? 7 b4 i/o st rc3 ? 8 a6 i/o st rc4 ? 9 b5 i/o st rc12 39 63 b34 i/o st rc13 47 73 a47 i/o st rc14 48 74 b40 i/o st rc15 40 64 a42 i/o st rd0 46 72 b39 i/o st portd is a bidirectional i/o port rd1 49 76 a52 i/o st rd2 50 77 b42 i/o st rd3 51 78 a53 i/o st rd4 52 81 b44 i/o st rd5 53 82 a55 i/o st rd6 54 83 b45 i/o st rd7 55 84 a56 i/o st rd8 42 68 b37 i/o st rd9 43 69 a45 i/o st rd10 44 70 b38 i/o st rd11 45 71 a46 i/o st rd12 ? 79 b43 i/o st rd13 ? 80 a54 i/o st rd14 ? 47 b26 i/o st rd15 ? 48 a31 i/o st table 1-1: pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = ttl input buffer note 1: this pin is available on pic32mx3xx devices only. 2: this pin is available on pic32mx4xx devices only.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 21 pic32mx330/350/370/430/450/470 re0 60 93 b52 i/o st porte is a bidirectional i/o port re1 61 94 a64 i/o st re2 62 98 a66 i/o st re3 63 99 b56 i/o st re4 64 100 a67 i/o st re5 1 3 b2 i/o st re6 2 4 a4 i/o st re7 3 5 b3 i/o st re8 ? 18 a11 i/o st re9 ? 19 b10 i/o st rf0 58 87 b49 i/o st portf is a bidirectional i/o port rf1 59 88 a60 i/o st rf2 34 (1) 52 a36 i/o st rf3 33 51 a35 i/o st rf4 31 49 b27 i/o st rf5 32 50 a32 i/o st rf6 35 (1) 55 (1) b30 (1) i/o st rf7 ? 54 (1) a37 (1) i/o st rf8 ? 53 b29 i/o st rf12 ? 40 a27 i/o st rf13 ? 39 b22 i/o st rg0 ? 90 a61 i/o st portg is a bidirectional i/o port rg1 ? 89 b50 i/o st rg2 (1) 37 57 b31 i/o st rg3 (1) 36 56 a38 i/o st rg6 4 10 a7 i/o st rg7 5 11 b6 i/o st rg8 6 12 a8 i/o st rg9 8 14 a9 i/o st rg12 ? 96 a65 i/o st rg13 ? 97 b55 i/o st rg14 ? 95 b54 i/o st rg15 ? 1 a2 i/o st t1ck 48 74 b40 i st timer1 external clock input t2ck pps pps pps i st timer2 external clock input t3ck pps pps pps i st timer3 external clock input t4ck pps pps pps i st timer4 external clock input t5ck pps pps pps i st timer5 external clock input table 1-1: pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = ttl input buffer note 1: this pin is available on pic32mx3xx devices only. 2: this pin is available on pic32mx4xx devices only.
pic32mx330/350/370/430/450/470 ds60001185b-page 22 preliminary ? 2012-2013 microchip technology inc. u1cts pps pps pps i st uart1 clear to send u1rts pps pps pps o ? uart1 ready to send u1rx pps pps pps i st uart1 receive u1tx pps pps pps o ? uart1 transmit u2cts pps pps pps i st uart2 clear to send u2rts pps pps pps o ? uart2 ready to send u2rx pps pps pps i st uart2 receive u2tx pps pps pps o ? uart2 transmit u3cts pps pps pps i st uart3 clear to send u3rts pps pps pps o ? uart3 ready to send u3rx pps pps pps i st uart3 receive u3tx pps pps pps o ? uart3 transmit u4cts pps pps pps i st uart4 clear to send u4rts pps pps pps o ? uart4 ready to send u4rx pps pps pps i st uart4 receive u4tx pps pps pps o ? uart4 transmit u5cts (3) pps pps pps i st uart5 clear to send u5rts (3) pps pps pps o ? uart5 ready to send u5rx (3) pps pps pps i st uart5 receive u5tx (3) pps pps pps o ? uart5 transmit sck1 35 (1) , 50 (2) 55 (1) , 70 (2) b30 (1) , b38 (2) i/o st synchronous serial clock input/output for spi1 sdi1 pps pps pps o ? spi1 data in sdo1 pps pps pps i/o st spi1 data out ss1 pps pps pps o ? spi1 slave synchronization for frame pulse i/o sck2 4 10 a7 i/o st synchronous serial clock input/output for spi2 sdi2 pps pps pps o ? spi2 data in sdo2 pps pps pps i/o st spi2 data out ss2 pps pps pps o ? spi2 slave synchronization for frame pulse i/o scl1 37 (1) , 44 (2) 57, 66 b31 (1) , b36 (2) i/o st synchronous serial clock input/output for i2c1 sda1 36 (1) , 43 (2) 56, 67 a38 (1) , a44 (2) i/o st synchronous serial data input/output for i2c1 scl2 32 58 a39 i/o st synchronous serial clock input/output for i2c2 sda2 31 59 b32 i/o st synchronous serial data input/output for i2c2 tms 23 17 b9 i st jtag test mode select pin tck 27 38 a26 i st jtag test clock input pin tdi 28 60 a40 i ? jtag test clock input pin tdo 24 61 b33 o ? jtag test clock output pin rtcc 42 68 b37 i st real-time clock alarm output table 1-1: pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = ttl input buffer note 1: this pin is available on pic32mx3xx devices only. 2: this pin is available on pic32mx4xx devices only.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 23 pic32mx330/350/370/430/450/470 cv ref - 15 28 a21 i analog comparator voltage reference (low) cv ref + 16 29 b17 i analog comparator voltage reference (high) cv refout 23 34 a24 i analog comparator voltage reference (output) c1ina 11 20 a12 i analog comparator 1 inputs c1inb 12 21 b11 i analog c1inc 5 11 b6 i analog c1ind 4 10 a7 i analog c2ina 13 22 a13 i analog comparator 2 inputs c2inb 14 23 b13 i analog c2inc 8 14 a9 i analog c2ind 6 12 a8 i analog c1out pps pps pps o ? comparator 1 output c2out pps pps pps o ? comparator 2 output pmall 30 44 a29 o ttl/st parallel master port address latch enable low byte pmalh 29 43 b24 o ttl/st parallel master port address latch enable high byte pma0 30 44 a29 o ttl/st parallel master port address bit 0 input (buffered slave modes) and output (master modes) pma1 29 43 b24 o ttl/st parallel master port address bit 0 input (buffered slave modes) and output (master modes) pma2 8 14 a9 o ttl/st parallel master port data (demultiplexed master mode) or address/data (multiplexed master modes) pma3 6 12 a8 o ttl/st pma4 5 11 b6 o ttl/st pma5 4 10 a7 o ttl/st pma6 16 29 b17 o ttl/st pma7 22 28 a21 o ttl/st pma8 32 50 a32 o ttl/st pma9 31 49 b27 o ttl/st pma10 28 42 a28 o ttl/st pma11 27 41 b23 o ttl/st pma12 24 35 b20 o ttl/st pma13 23 34 a24 o ttl/st pma14 45 71 a46 o ttl/st pma15 44 70 b38 o ttl/st pmcs1 45 71 a46 o ttl/st pmcs2 44 72 b38 o ttl/st pmd0 60 93 b52 o ttl/st pmd1 61 94 a64 o ttl/st pmd2 62 98 a66 o ttl/st table 1-1: pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = ttl input buffer note 1: this pin is available on pic32mx3xx devices only. 2: this pin is available on pic32mx4xx devices only.
pic32mx330/350/370/430/450/470 ds60001185b-page 24 preliminary ? 2012-2013 microchip technology inc. pmd3 63 99 b56 o ttl/st parallel master port data (demultiplexed master mode) or address/data (multiplexed master modes) pmd4 64 100 a67 o ttl/st pmd5 1 3 b2 o ttl/st pmd6 2 4 a4 o ttl/st pmd7 3 5 b3 o ttl/st pmd8 ? 90 a61 o ttl/st pmd9 ? 89 b50 o ttl/st pmd10 ? 88 a60 o ttl/st pmd11 ? 87 b49 o ttl/st pmd12 ? 79 b43 o ttl/st pmd13 ? 80 a54 o ttl/st pmd14 ? 83 b45 o ttl/st pmd15 ? 84 a56 o ttl/st pmrd 53 82 a55 o ? parallel master port read strobe pmwr 52 81 b44 o ? parallel master port write strobe v bus (2) 34 54 a37 i analog usb bus power monitor v usb 3 v 3 (2) 35 55 b30 p ? usb internal transceiver supply. if the usb module is not used, this pin must be connected to v dd . v buson (2) 11 20 a12 o ? usb host and otg bus power control output d+ (2) 37 57 b31 i/o analog usb d+ d- (2) 36 56 a38 i/o analog usb d- usbid (2) 33 51 a35 i st usb otg id detect pged1 16 25 b14 i/o st data i/o pin for programming/debugging communication channel 1 pgec1 15 24 a15 i st clock input pin for programming/debugging communication channel 1 pged2 18 27 b16 i/o st data i/o pin for programming/debugging communication channel 2 pgec2 17 26 a20 i st clock input pin for programming/debugging communication channel 2 pged3 13 22 a13 i/o st data i/o pin for programming/debugging communication channel 3 pgec3 14 23 b13 i st clock input pin for programming/debugging communication channel 3 tck 27 38 a26 i st jtag test clock input pin tms 23 17 b9 i st jtag test mode select pin tdi 28 60 a40 i st jtag test data input pin tdo 24 61 b33 o ? jtag test data output pin trclk 59 91 b51 o ? trace clock trd0 60 97 b55 o ? trace data bit 0 trd1 61 96 a65 o ? trace data bit 1 trd2 62 95 b54 o ? trace data bit 2 trd3 63 92 a62 o ? trace data bit 3 table 1-1: pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = ttl input buffer note 1: this pin is available on pic32mx3xx devices only. 2: this pin is available on pic32mx4xx devices only.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 25 pic32mx330/350/370/430/450/470 cted1 ? 17 b9 i st ctmu external edge input 1 cted2 ? 38 a26 i st ctmu external edge input 2 cted3 18 27 b16 i st ctmu external edge input 3 cted4 22 33 b19 i st ctmu external edge input 4 cted5 29 43 b24 i st ctmu external edge input 5 cted6 30 44 a29 i st ctmu external edge input 6 cted7 ? 9 b5 i st ctmu external edge input 7 cted8 ? 92 a62 i st ctmu external edge input 8 cted9 ? 60 a40 i st ctmu external edge input 9 cted10 21 32 a23 i st ctmu external edge input 10 cted11 23 34 a24 i st ctmu external edge input 11 cted12 15 24 a15 i st ctmu external edge input 12 cted13 14 23 b13 i st ctmu external edge input 13 mclr 7 13 b7 i/p st master clear (reset) input. this pin is an active-low reset to the device. av dd 19 30 a22 p p positive supply for analog modules. this pin must be connected at all times. av ss 20 31 b18 p p ground reference for analog modules v dd 10, 26, 38, 57 2, 16, 37, 46, 62, 86 b1, a10, a14, b21, a30, a41, a48, a59, b53 p ? positive supply for peripheral logic and i/o pins v cap 56 85 b48 p ? capacitor for internal voltage regulator v ss 9, 25, 41 15, 36, 45, 65, 75 a3, b8, b12, a25, b25, a43, b41, a63 p ? ground reference for logic and i/o pins v ref + 16 29 b17 i analog analog voltage reference (high) input v ref - 15 28 a21 i analog analog voltage reference (low) input table 1-1: pinout i/o descriptions (continued) pin name pin number pin type buffer type description 64-pin qfn/ tqfp 100-pin tqfp 124-pin vtla legend: cmos = cmos compatible input or output analog = analog input p = power ? st = schmitt trigger input with cmos levels o = output i = input ? ttl = ttl input buffer note 1: this pin is available on pic32mx3xx devices only. 2: this pin is available on pic32mx4xx devices only.
pic32mx330/350/370/430/450/470 ds60001185b-page 26 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 27 pic32mx330/350/370/430/450/470 2.0 guidelines for getting started with 32-bit mcus 2.1 basic connection requirements getting started with the pic32mx330/350/370/430/ 450/470 family of 32-bit microcontrollers (mcus) requires attention to a minimal set of device pin con - nections before proceeding with development. the fol - lowing is a list of pin names, which must always be connected: ? all v dd and v ss pins (see 2.2 ?decoupling capac - itors? ) ? all av dd and av ss pins, even if the adc module is not used (see 2.2 ?decoupling capacitors? ) ?v cap pin (see 2.3 ?capacitor on internal voltage regulator (v cap )? ) ? mclr pin (see 2.4 ?master clear (mclr) pin? ) ? pgecx/pgedx pins, used for in-circuit serial pro - gramming (icsp?) and debugging purposes (see 2.5 ?icsp pins? ) ? osc1 and osc2 pins, when external oscillator source is used (see 2.8 ?external oscillator pins? ) the following pin may be required, as well: v ref +/v ref - pins, used when external voltage reference for the adc module is implemented . 2.2 decoupling capacitors the use of decoupling capacitors on power supply pins, such as v dd , v ss , av dd and av ss is required. see figure 2-1 . consider the following criteria when using decoupling capacitors: ? value and type of capacitor: a value of 0.1 f (100 nf), 10-20v is recommended. the capacitor should be a low equivalent series resistance (low- esr) capacitor and have resonance frequency in the range of 20 mhz and higher. it is further recommended that ceramic capacitors be used. ? placement on the printed circuit board: the decoupling capacitors should be placed as close to the pins as possible. it is recommended that the capacitors be placed on the same side of the board as the device. if space is constricted, the capacitor can be placed on another layer on the pcb using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. ? handling high frequency noise: if the board is experiencing high frequency noise, upward of tens of mhz, add a second ceramic-type capacitor in par - allel to the above described decoupling capacitor. the value of the second capacitor can be in the range of 0.01 f to 0.001 f. place this second capacitor next to the prim ary decoupling capacitor. in high-speed circuit designs, consider implement - ing a decade pair of capacitances as close to the power and ground pins as possible. for example, 0.1 f in parallel with 0.001 f. ? maximizing performance: on the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. this ensures that the decou - pling capacitors are first in the power chain. equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing pcb track inductance. note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to the related section of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. note: the av dd and av ss pins must be connected, regardless of adc use and the adc voltage reference source.
pic32mx330/350/370/430/450/470 ds60001185b-page 28 preliminary ? 2012-2013 microchip technology inc. figure 2-1: recommended minimum connection 2.2.1 bulk capacitors the use of a bulk capacitor is recommended to improve power supply stability. typica l values range from 4.7 f to 47 f. this capacitor should be located as close to the device as possible. 2.3 capacitor on internal voltage regulator (v cap ) 2.3.1 internal regulator mode a low-esr (1 ohm) capaci tor is required on the v cap pin, which is used to stabilize the internal voltage regu - lator output. the v cap pin must not be connected to v dd , and must have a c efc capacitor, with at least a 6v rating, connected to ground. the type can be ceramic or tantalum. refer to section 30.0 ?electrical characteristics? for additional information on c efc specifications. 2.4 master clear ( mclr ) pin the mclr pin provides for two specific device functions: ? device reset ? device programming and debugging pulling the mclr pin low generates a device reset. figure 2-2 illustrates a typical mclr circuit. during device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. device programmers and debuggers drive the mclr pin. consequently, specific voltage levels (v ih and v il ) and fast signal transitions must not be adversely affected. t herefore, specific values of r and c will need to be adjusted based on the application and pcb requirements. for example, as illustrated in figure 2-2 , it is recommended that the capacito r c, be isolated from the mclr pin during programming and debugging operations. place the components illustrated in figure 2-2 within one-quarter inch (6 mm) from the mclr pin. figure 2-2: example of mclr pin connections pic32 v dd v ss v dd v ss v ss v dd av dd av ss v dd v ss 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic 0.1 f ceramic c r v dd mclr 0.1 f ceramic l1 (2) r1 note 1: if the usb module is not used, this pin must be connected to v dd . 2: as an option, instead of a hard-wired connection, an inductor (l1) can be substituted between v dd and av dd to improve adc noise rejection. the inductor impedance should be less than 1 ? and the inductor capacity greater than 10 ma. ? ? where: f f cnv 2 ------------- - = f 1 2 ? lc ?? ----------------------- = l 1 2 ? fc ?? --------------------- - ?? ?? 2 = (i.e., adc conversion rate/2) connect (2) v usb 3 v 3 (1) note 1: r ? 10 k ? is recommended. a suggested starting value is 10 k ? . ensure that the mclr pin v ih and v il specifications are met. 2: r1 ? 470 ? will limit any current flowing into mclr from the external capacitor c, in the event of mclr pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). ensure that the mclr pin v ih and v il specifications are met. 3: the capacitor can be sized to prevent uninten- tional resets from brief glitches or to extend the device reset period during por. c (3) r1 (2) r (1) v dd mclr pic32 jp
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 29 pic32mx330/350/370/430/450/470 2.5 icsp pins the pgecx and pgedx pins are used for in-circuit serial programming? (icsp?) and debugging pur - poses. it is recommended to keep the trace length between the icsp connector and the icsp pins on the device as short as possible. if the icsp connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the pgecx and pgedx pins are not recommended as they will interfere with the programmer/debugger communi - cations to the device. if such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. alternatively, refer to t he ac/dc characteristics and timing requirements information in the respective device flash programming spec ification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. ensure that the ?communication channel select? (i.e., pgecx/pgedx pins) programmed into the device matches the physical con nections for the icsp to mplab ? icd 3 or mplab real ice?. for more information on icd 3 and real ice connection requirements, refer to the following documents that are available on the microchip web site. ? ?using mplab ? icd 3? (poster) ds50001765 ? ?mplab ? icd 3 design advisory? ds50001764 ? ?mplab ? real ice? in-circuit debugger user?s guide? ds50001616 ? ?using mplab ? real ice? emulator? (poster) ds50001749 2.6 jtag the tms, tdo, tdi and tck pins are used for testing and debugging according to the joint test action group (jtag) standard. it is recommended to keep the trace length between the jtag connector and the jtag pins on the device as short as possible. if the jtag connector is expected to experience an esd event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100 ohms. pull-up resistors, series diodes and capacitors on the tms, tdo, tdi and tck pins are not recommended as they will interfere with the programmer/debugger communications to the device . if such discrete compo - nents are an application requi rement, they should be removed from the circuit during programming and debugging. alternatively, re fer to the ac/dc character - istics and timing requirements information in the respective device flash prog ramming specification for information on capacitive loading limits and pin input voltage high (v ih ) and input low (v il ) requirements. 2.7 trace the trace pins can be connected to a hardware trace-enabled programmer to provide a compressed real-time instruction trace. when used for trace, the trd3, trd2, trd1, trd0 and trclk pins should be dedicated for this use. the trace hardware requires a 22 ohm series resistor between the trace pins and the trace connector. 2.8 external oscillator pins many mcus have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to section 8.0 ?oscillator configuration? for details). the oscillator circuit should be placed on the same side of the board as the device. also, place the oscillator cir - cuit close to the respective oscillator pins, not exceed - ing one-half inch (12 mm) distance between them. the load capacitors should be placed next to the oscillator itself, on the same side of the board. use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. the grounded copper pour should be routed directly to the mcu ground. do not run any signal traces or pow er traces inside the ground pour. also, if using a two-si ded board, avoid any traces on the other side of the board where the crystal is placed. a suggested layo ut is illustrated in figure 2-3 . figure 2-3: suggested oscillator circuit placement 2.9 unused i/os unused i/o pins should not be allowed to float as inputs. they can be configured as outputs and driven to a logic-low state. alternatively, inputs can be reserved by connecting the pin to v ss through a 1k to 10k resistor and configuring the pin as an input. main oscillator guard ring guard trace secondary oscillator
pic32mx330/350/370/430/450/470 ds60001185b-page 30 preliminary ? 2012-2013 microchip technology inc. 2.10 typical application connection examples examples of typical application connections are shown in figure 2-4 and figure 2-5 . figure 2-4: capacitive touch sensing with graphics application figure 2-5: audio playback application ctmu current source adc microchip mtouch? library user application microchip graphics library read the touch sensors process samples display data parallel master port lcd controller frame buffer display controller pmd<7:0> lcd panel pic32mx430f064l to an6 to an7 to an8 to an11 c1 r3 c2 r2 r3 r1 c5 c5 c5 c1 r1 r1 r1 c3 r2 c3 r2 c1 r2 c2 r3 c2 r3 c3 an0 an1 an11 to a n 0 to a n 1 to an 5 an9 pmwr to a n 9 r1 c4 r2 c4 r3 c4 audio codec display pmp i 2 s spi usb usb pmd<7:0> 3 3 stereo headphones speaker pic32mx450f256l host pmwr mmc sd 3 sdi refclko
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 31 pic32mx330/350/370/430/450/470 figure 2-6: low-cost co ntrollerless (lcc) graphi cs application with projected capacitive touch lcd display pic32mx430f064l sram ctmu microchip mtouch? dma pmp adc projected capacitive touch overlay gfx libraries external frame buffer anx
pic32mx330/350/370/430/450/470 ds60001185b-page 32 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 33 pic32mx330/350/370/430/450/470 3.0 cpu the the mips32 ? m4k ? processor core is the heart of the pic32mx330/350/370/ 430/450/470 device proces - sor. the cpu fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes t he results of instruction execution to the proper destinations. 3.1 features ? 5-stage pipeline ? 32-bit address and data paths ? mips32 ? enhanced architecture (release 2): - multiply-accumulate and multiply-subtract instructions - targeted multiply instruction - zero/one detect instructions - wait instruction - conditional move instructions ( movn , movz ) - vectored interrupts - programmable exception vector base - atomic interrupt enable/disable - gpr shadow registers to minimize latency for interrupt handlers - bit field manipulation instructions ? mips16e ? code compression: - 16-bit encoding of 32-bit instructions to improve code density - special pc-relative instructions for efficient loading of addresses and constants - save and restore macro instructions for setting up and tearing down stack frames within subroutines - improved support for handling 8 and 16-bit data types ? simple fixed mapping translation (fmt) ? mechanism: ? simple dual bus interface: - independent 32-bit address and data busses - transactions can be aborted to improve interrupt latency ? autonomous multiply /divide unit (mdu): - maximum issue rate of one 32x16 multiply per clock - maximum issue rate of one 32x32 multiply every other clock - early-in iterative divide. minimum 11 and maximum 33 clock latency (dividend ( rs ) sign extension-dependent) ? power control: - minimum frequency: 0 mhz - low-power mode (triggered by wait instruction) - extensive use of local gated clocks ? ejtag debug and instruction trace: - support for single stepping - virtual instruction and data address/value - breakpoints figure 3-1: mips32 ? m4k ? processor core block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 2. ?cpu? (ds60001113) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). resources for the mips32 ? m4k ? processor core are available at http://www.mips.com . 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. cpu mdu execution core (rf/alu/shift) fmt tap ejtag bus interface power management system co-processor off-chip debug interface bus matrix dual bus interface
pic32mx330/350/370/430/450/470 ds60001185b-page 34 preliminary ? 2012-2013 microchip technology inc. 3.2 architecture overview the mips32 ? m4k ? processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. the following blocks are in cluded with the core: ? execution unit ? multiply/divide unit (mdu) ? system control coprocessor (cp0) ? fixed mapping translation (fmt) ? dual internal bus interfaces ? power management ? mips16e ? support ? enhanced jtag (ejtag) controller 3.2.1 execution unit the mips32 ? m4k ? processor core execution unit implements a load/store architecture with single-cycle alu operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. the core contains thirty-two 32-bit general purpose registers (gprs) used for integer operations and address calculation. one additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during in terrupt/exception process - ing. the register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. the execution unit includes: ? 32-bit adder used for calculating the data address ? address unit for calculating the next instruction address ? logic for branch determination and branch target address calculation ? load aligner ? bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results ? leading zero/one detect unit for implementing the clz and clo instructions ? arithmetic logic unit (alu) for performing bitwise logical operations ? shifter and store aligner 3.2.2 multiply/divide unit (mdu) the mips32 ? m4k ? processor core includes a multi - ply/divide unit (mdu) that co ntains a separate pipeline for multiply and divide operations. this pipeline oper - ates in parallel with the int eger unit (iu) pipeline and does not stall when the iu pipeline stalls. this allows mdu operations to be partially masked by system stalls and/or other integer unit instructions. the high-performance mdu consists of a 32x16 booth recoded multiplier, result/accumulation registers (hi and lo), a divide state machine, and the necessary multiplexers and control logic. the first number shown (?32? of 32x16) represents the rs operand. the second number (?16? of 32x16) represents the rt operand. the pic32 core only checks the value of the latter ( rt) oper - and to determine how many times the operation must pass through the multiplier. the 16x16 and 32x16 operations pass through the multiplier once. a 32x32 operation passes through the multiplier twice. the mdu supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. the multiply operand size is automatically determined by logic built into the mdu. divide operations are implemented with a simple 1 bit per clock iterative algorith m. an early-in detection checks the sign extension of the dividend ( rs ) operand. if rs is 8 bits wide, 23 iterations are skipped. for a 16-bit wide rs , 15 iterations are skipped and for a 24-bit wide rs , 7 iterations are skipped. any attempt to issue a sub - sequent mdu instruction while a divide is still active causes an iu pipeline stall until the divide operation is completed. table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (num - ber of cycles until a result is available) for the pic32 core multiply and divide in structions. the approximate latency and repeat rates are listed in terms of pipeline clocks. table 3-1: mips32 ? m4k ? processor core high-performance integer multiply/ divide unit latencies and repeat rates op code operand size (mul rt ) (div rs ) latency repeat rate mult/multu, madd/maddu, msub/msubu 16 bits 1 1 32 bits 2 2 mul 16 bits 2 1 32 bits 3 2 div/divu 8 bits 12 11 16 bits 19 18 24 bits 26 25 32 bits 33 32
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 35 pic32mx330/350/370/430/450/470 the mips architecture defines that the result of a multiply or divide operation be placed in the hi and lo registers. using the move-from-hi ( mfhi ) and move- from-lo ( mflo ) instructions, these values can be transferred to the general purpose register file. in addition to the hi/lo targeted operations, the mips32 ? architecture also defines a multiply instruction, mul , which places the least significant results in the pri - mary register file instead of the hi/lo register pair. by avoiding the explicit mflo instruction required when using the lo register, and by supporting multiple desti - nation registers, the throu ghput of multiply-intensive operations is increased. two other instructions, multiply-add ( madd ) and multiply-subtract ( msub ), are used to perform the multiply-accumulate and multiply-subtract operations. the madd instruction multiplies two numbers and then adds the product to the current contents of the hi and lo registers. similarly, the msub instruction multiplies two operands and then subtra cts the product from the hi and lo registers. the madd and msub operations are commonly used in dsp algorithms. 3.2.3 system control ? coprocessor (cp0) in the mips architecture, cp0 is responsible for the virtual-to-physical address translation, the exception control system, the processor?s diagnostics capability, the operating modes (kernel, user and debug) and whether interrupts are enabled or disabled. configura - tion information, such as presence of options like mips16e ? , is also available by accessing the cp0 registers, listed in ta b l e 3-2 . table 3-2: coprocessor 0 registers register number register name function 0-6 reserved reserved in the pic32mx330/3 50/370/430/450/470 family core. 7 hwrena enables access via the rdhwr instruction to select ed hardware registers. 8 badvaddr (1) reports the address for the most recent address-related exception. 9 count (1) processor cycle count. 10 reserved reserved in the pic32mx330/3 50/370/430/450/470 family core. 11 compare (1) timer interrupt control. 12 status (1) processor status and control. 12 intctl (1) interrupt system status and control. 12 srsctl (1) shadow register set status and control. 12 srsmap (1) provides mapping from vectored interrupt to a shadow set. 13 cause (1) cause of last general exception. 14 epc (1) program counter at last exception. 15 prid processor identification and revision. 15 ebase exception vector base register. 16 config configuration register. 16 config1 configuration register 1. 16 config2 configuration register 2. 16 config3 configuration register 3. 17-22 reserved reserved in the pic32mx330/3 50/370/430/450/470 family core. 23 debug (2) debug control and exception status. 24 depc (2) program counter at last debug exception. 25-29 reserved reserved in the pic32mx330/3 50/370/430/450/470 family core. 30 errorepc (1) program counter at last error. 31 desave (2) debug handler scratchpad register. note 1: registers used in exception processing. 2: registers used during debug.
pic32mx330/350/370/430/450/470 ds60001185b-page 36 preliminary ? 2012-2013 microchip technology inc. coprocessor 0 also contains the logic for identifying and managing exceptions. exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. table 3-3 lists the exception types in order of priority. table 3-3: mips32 ? m4k ? processor core exception types 3.3 power management the mips ? m4k ? processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. the core is a static design that supports slowing or halting the clocks, which reduces system power consumpti on during idle periods. 3.3.1 instruction-controlled power management the mechanism for invoking power-down mode is through execution of the wait instruction. for more information on power management, see section 26.0 ?power-saving features? . 3.3.2 local clock gating the majority of the power consumed by the pic32mx330/350/370/430/450/470 family core is in the clock tree and clocking registers. the pic32mx family uses extensive use of local gated-clocks to reduce this dynamic power consumption. 3.4 ejtag debug support the mips ? m4k ? processor core provides for an enhanced jtag (ejtag) inte rface for use in the soft - ware debug of application and kernel code. in addition to standard user mode and ke rnel modes of operation, the m4k ? core provides a debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a debug exception return ( deret ) instruction is executed. duri ng this time, the processor executes the debug exception handler routine. the ejtag interface operates through the test access port (tap), a serial communication port used for trans - ferring test data in and out of the core. in addition to the standard jtag instructio ns, special instructions defined in the ejtag spec ification define which registers are selected and how they are used. exception description reset assertion mclr or a power-on reset (por). dss ejtag debug single step. dint ejtag debug interrupt. caused by the assertion of the external ej_dint input or by setting the ejtagbrk bit in the ecr register. nmi assertion of nmi signal. interrupt assertion of unmasked hardware or software interrupt signal. dib ejtag debug hardware instruction break matched. adel fetch address alignment error. fetch reference to protected address. ibe instruction fetch bus error. dbp ejtag breakpoint (execution of sdbbp instruction). sys execution of syscall instruction. bp execution of break instruction. ri execution of a reserved instruction. cpu execution of a coprocessor instruction for a coprocessor that is not enabled. ceu execution of a corextend instruction when corextend is not enabled. ov execution of an arithmetic instruction that overflowed. tr execution of a trap (when trap condition is true). ddbl/ddbs ejtag data address break (address only) or ej tag data value break on store (address + value). adel load address alignment error. load reference to protected address. ades store address alignment error. store to protected address. dbe load or store bus error. ddbl ejtag data hardware breakpoint matched in load data compare.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 37 pic32mx330/350/370/430/450/470 4.0 memory organization pic32mx330/350/370/430/450 /470 microcontrollers provide 4 gb of unified virtual memory address space. all memory regions, including program, data memory, sfrs and configuration registers, reside in this address space at their respective unique addresses. the program and data memories can be optionally par - titioned into user and kernel memories. in addition, the data memory can be made executable, allowing pic32mx330/350/370/430/450/4 70 devices to execute from data memory. key features include: ? 32-bit native data width ? separate user (kuseg) and kernel (kseg0/ kseg1) mode address space ? flexible program flash memory partitioning ? flexible data ram partitioning for data and program space ? separate boot flash memory for protected code ? robust bus exception handling to intercept ? runaway code ? simple memory mapping with fixed mapping translation (fmt) unit ? cacheable (kseg0) and non-cacheable (kseg1) address regions 4.1 memory layout pic32mx330/350/370/430/45 0/470 microcontrollers implement two address schemes: virtual and physical. all hardware resources, su ch as program memory, data memory and peripherals, are located at their respective physical addre sses. virtual addresses are exclusively used by the cpu to fetch and execute instructions as well as access peripherals. physical addresses are used by bus master peripherals, such as dma and the flash controll er, that access memory independently of the cpu. the memory maps for the pic32mx330/350/370/430/ 450/470 devices are illustrated in figure 4-1 through figure 4-3 . note: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/470 family of devices. it is not intended to be a comprehensive reference source.for detailed information, refer to section 3. ?memory organization? (ds60001115) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ).
pic32mx330/350/370/430/450/470 ds60001185b-page 38 preliminary ? 2012-2013 microchip technology inc. figure 4-1: memory map for devic es with 64 kb of program memory virtual memory map (1) physical memory map (1) 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd010000 0xbd00ffff program flash (2) 0xbd000000 reserved 0xa0004000 0xa0003fff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d010000 0x1f800000 0x9d00ffff program flash (2) reserved 0x9d000000 0x1d010000 reserved program flash (2) 0x1d00ffff 0x80004000 0x80003fff ram (2) 0x1d000000 reserved 0x80000000 0x00004000 reserved ram (2) 0x00003fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds60001115) in the ?pic32 family reference manual? ) and can be changed by initializa- tion code provided by end-user dev elopment tools (refer to the specific development tool documentation for information). kseg1 kseg0
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 39 pic32mx330/350/370/430/450/470 figure 4-2: memory map for devices with 128 kb of program memory virtual memory map (1) physical memory map (1) 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd020000 0xbd01ffff program flash (2) 0xbd000000 reserved 0xa0008000 0xa0007fff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d020000 0x1f800000 0x9d01ffff program flash (2) reserved 0x9d000000 0x1d020000 reserved program flash (2) 0x1d01ffff 0x80008000 0x80007fff ram (2) 0x1d000000 reserved 0x80000000 0x00008000 reserved ram (2) 0x00007fff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds60001115) in the ?pic32 family reference manual? ) and can be changed by initializa- tion code provided by end-user dev elopment tools (refer to the specific development tool documentation for information). kseg1 kseg0
pic32mx330/350/370/430/450/470 ds60001185b-page 40 preliminary ? 2012-2013 microchip technology inc. figure 4-3: memory map for devices with 256 kb of program memory virtual memory map (1) physical memory map (1) 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd040000 0xbd03ffff program flash (2) 0xbd000000 reserved 0xa0010000 0xa000ffff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d040000 0x1f800000 0x9d03ffff program flash (2) reserved 0x9d000000 0x1d040000 reserved program flash (2) 0x1d03ffff 0x80010000 0x8000ffff ram (2) 0x1d000000 reserved 0x80000000 0x00010000 reserved ram (2) 0x0000ffff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds60001115) in the ?pic32 family reference manual? ) and can be changed by initializa- tion code provided by end-user dev elopment tools (refer to the specific development tool documentation for information). kseg1 kseg0
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 41 pic32mx330/350/370/430/450/470 figure 4-4: memory map for devices with 512 kb of program memory virtual memory map (1) physical memory map (1) 0xffffffff reserved reserved 0xffffffff 0xbfc03000 0xbfc02fff device configuration registers 0xbfc02ff0 0xbfc02fef boot flash 0xbfc00000 reserved 0xbf900000 0xbf8fffff sfrs 0xbf800000 reserved 0xbd080000 0xbd07ffff program flash (2) 0xbd000000 reserved 0xa0020000 0xa001ffff ram (2) 0xa0000000 0x1fc03000 reserved device configuration registers 0x1fc02fff 0x9fc03000 0x9fc02fff device configuration registers 0x1fc02ff0 boot flash 0x1fc02fef 0x9fc02ff0 0x9fc02fef boot flash 0x1fc00000 reserved 0x9fc00000 0x1f900000 reserved sfrs 0x1f8fffff 0x9d080000 0x1f800000 0x9d07ffff program flash (2) reserved 0x9d000000 0x1d080000 reserved program flash (2) 0x1d07ffff 0x80020000 0x8001ffff ram (2) 0x1d000000 reserved 0x80000000 0x00020000 reserved ram (2) 0x0001ffff 0x00000000 0x00000000 note 1: memory areas are not shown to scale. 2: the size of this memory region is programmable (see section 3. ?memory organization? (ds60001115) in the ?pic32 family reference manual? ) and can be changed by initializa- tion code provided by end-user dev elopment tools (refer to the specific development tool documentation for information). kseg1 kseg0
pic32mx330/350/370/430/450/470 ds60001185b-page 42 preliminary ? 2012-2013 microchip technology inc. 4.2 special function register maps table 4-1 through ta b l e 4-39 contain the peripheral addres s maps for the pic32mx330/350/370/430/450/470 devices. table 4-1: bus matrix register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 bmxcon (1) 31:16 ? ? ? ? ? bmxchedma ? ? ? ? ? bmxerrixi bmxerricd bmxerrdma bmxerrds bmxerris 041f 15:0 ? ? ? ? ? ? ? ? ?bmxwsdrm ? ? ? bmxarb<2:0> 0047 2010 bmxdkpba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdkpba<15:0> 0000 2020 bmxdudba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdudba<15:0> 0000 2030 bmxdupba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 bmxdupba<15:0> 0000 2040 bmxdrmsz 31:16 bmxdrmsz<31:0> xxxx 15:0 xxxx 2050 bmxpupba (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? bmxpupba<19:16> 0000 15:0 bmxpupba<15:0> 0000 2060 bmxpfmsz 31:16 bmxpfmsz<31:0> xxxx 15:0 xxxx 2070 bmxbootsz 31:16 bmxbootsz<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at it s virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 43 pic32mx330/350/370/430/450/470 table 4-2: interrupt register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 intcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ss0 0000 15:0 ? ? ? mvec ?tpc<2:0> ? ? ? int4ep int3ep int2ep int1ep int0ep 0000 1010 intstat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ?sripl<2:0> ? ? vec<5:0> 0000 1020 iptmr 31:16 iptmr<31:0> 0000 15:0 0000 1030 ifs0 31:16 fceif rtccif fscmif ad1if oc5if ic5if ic5eif t5i f int4if oc4if ic4if ic4eif t4if int3if oc3if ic3if 0000 15:0 ic3eif t3if int2if oc2if ic2if ic2eif t2if int1 if oc1if ic1if ic1eif t1if int0if cs1if cs0if ctif 0000 1040 ifs1 31:16 u3rxif u3eif i2c2mif i2c2sif i2c2bif u2txif u2rxif u 2eif spi2txif spi2rxif spi2eif pmpeif pmpif cngif cnfif cneif 0000 15:0 cndif cncif cnbif cnaif i2c1mif i2c1sif i2c1bif u1txif u1rxif u1eif spi1txif spi1rxif spi1eif usbif (2) cmp2if cmp1if 0000 1050 ifs2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? dma3if dma2if dma1if dma0if ctmuif u5txif (1) u5rxif (1) u5eif (1) u4txif u4rxif u4eif u3txif 0000 1060 iec0 31:16 fceie rtccie fscmie ad1ie oc5ie ic5ie ic5eie t5i e int4ie oc4ie ic4ie ic4eie t4ie int3ie oc3ie ic3ie 0000 15:0 ic3eie t3ie int2ie oc2ie ic2ie ic2eie t2ie int1 ie oc1ie ic1ie ic1eie t1ie int0ie cs1ie cs0ie ctie 0000 1070 iec1 31:16 u3rxie u3eie i2c2mie i2c2sie i2c2bie u2txie u2rxie u2eie spi2txie spi2rxie spi2eie pmpeie pmpie cngie cnfie cneie 0000 15:0 cndie cncie cnbie cnaie i2c1mie i2c1sie i2c1bie u 1txie u1rxie u1eie spi1txie spi1rxie spi1eie usbie (2) cmp2ie cmp1ie 0000 1080 iec2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? dma3ie dma2ie dma1ie dma0ie ctmuie u5txie (1) u5rxie (1) u5eie (1) u4txie u4rxie u4eie u3txie 0000 1090 ipc0 31:16 ? ? ? int0ip<2:0> int0is<1:0> ? ? ? cs1ip<2:0> cs1is<1:0> 0000 15:0 ? ? ? cs0ip<2:0> cs0is<1:0> ? ? ? ctip<2:0> ctis<1:0> 0000 10a0 ipc1 31:16 ? ? ? int1ip<2:0> int1is<1:0> ? ? ? oc1ip<2:0> oc1is<1:0> 0000 15:0 ? ? ? ic1ip<2:0> ic1is<1:0> ? ? ? t1ip<2:0> t1is<1:0> 0000 10b0 ipc2 31:16 ? ? ? int2ip<2:0> int2is<1:0> ? ? ? oc2ip<2:0> oc2is<1:0> 0000 15:0 ? ? ? ic2ip<2:0> ic2is<1:0> ? ? ? t2ip<2:0> t2is<1:0> 0000 10c0 ipc3 31:16 ? ? ? int3ip<2:0> int3is<1:0> ? ? ? oc3ip<2:0> oc3is<1:0> 0000 15:0 ? ? ? ic3ip<2:0> ic3is<1:0> ? ? ? t3ip<2:0> t3is<1:0> 0000 10d0 ipc4 31:16 ? ? ? int4ip<2:0> int4is<1:0> ? ? ? oc4ip<2:0> oc4is<1:0> 0000 15:0 ? ? ? ic4ip<2:0> ic4is<1:0> ? ? ? t4ip<2:0> t4is<1:0> 0000 10e0 ipc5 31:16 ? ? ? ad1ip<2:0> ad1is<1:0> ? ? ? oc5ip<2:0> oc5is<1:0> 0000 15:0 ? ? ? ic5ip<2:0> ic5is<1:0> ? ? ? t5ip<2:0> t5is<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this bit is available on pic32mx3xxfxxxl devices only.
pic32mx330/350/370/430/450/470 ds60001185b-page 44 preliminary ? 2012-2013 microchip technology inc. 10f0 ipc6 31:16 ? ? ? cmp1ip<2:0> cmp1is<1:0> ? ? ? fceip<2:0> fceis<1:0> 0000 15:0 ? ? ? rtccip<2:0> rtccis<1:0> ? ? ? fscmip<2:0> fscmis<1:0> 0000 1100 ipc7 31:16 ? ? ? u1ip<2:0> u1is<1:0> ? ? ? spi1ip<2:0> (2) spi1is<1:0> (2) 0000 15:0 ? ? ? usbip<2:0> usbis<1:0> ? ? ? cmp2ip<2:0> cmp2is<1:0> 0000 1110 ipc8 31:16 ? ? ? spi2ip<2:0> spi2is<1:0> ? ? ? pmpip<2:0> pmpis<1:0> 0000 15:0 ? ? ? cnip<2:0> cnis<1:0> ? ? ? i2c1ip<2:0> i2c1is<1:0> 0000 1120 ipc9 31:16 ? ? ? u4ip<2:0> u4is<1:0> ? ? ? u3ip<2:0> u3is<1:0> 0000 15:0 ? ? ? i2c2ip<2:0> i2c2is<1:0> ? ? ? u2ip<2:0> u2is<1:0> 0000 1130 ipc10 31:16 ? ? ? dma1ip<2:0> dma1is<1:0> ? ? ? dma0ip<2:0> dma0is<1:0> 0000 15:0 ? ? ? ctmuip<2:0> ctmuis<1:0> ? ? ? u5ip<2:0> u5is<1:0> 0000 1140 ipc11 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? dma3ip<2:0> dma3is<1:0> ? ? ? dma2ip<2:0> dma2is<1:0> 0000 table 4-2: interrupt register map (continued) virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this bit is available on pic32mx3xxfxxxl devices only.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 45 pic32mx330/350/370/430/450/470 table 4-3: timer1 through timer5 register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0600 t1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl twdis twip ? ? ?tgate ?tckps<1:0> ?tsynctcs ? 0000 0610 tmr1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr1<15:0> 0000 0620 pr1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr1<15:0> ffff 0800 t2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> t32 ?tcs ? 0000 0810 tmr2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr2<15:0> 0000 0820 pr2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr2<15:0> ffff 0a00 t3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> ? ?tcs ? 0000 0a10 tmr3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr3<15:0> 0000 0a20 pr3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr3<15:0> ffff 0c00 t4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> t32 ?tcs ? 0000 0c10 tmr4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr4<15:0> 0000 0c20 pr4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr4<15:0> ffff 0e00 t5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? tgate tckps<2:0> ? ?tcs ? 0000 0e10 tmr5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 tmr5<15:0> 0000 0e20 pr5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pr5<15:0> ffff legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 46 preliminary ? 2012-2013 microchip technology inc. table 4-4: input capture 1 through input capture 5 register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 ic1con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2010 ic1buf 31:16 ic1buf<31:0> xxxx 15:0 xxxx 2200 ic2con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2210 ic2buf 31:16 ic2buf<31:0> xxxx 15:0 xxxx 2400 ic3con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2410 ic3buf 31:16 ic3buf<31:0> xxxx 15:0 xxxx 2600 ic4con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2610 ic4buf 31:16 ic4buf<31:0> xxxx 15:0 xxxx 2800 ic5con (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? fedge c32 ictmr ici<1:0> icov icbne icm<2:0> 0000 2810 ic5buf 31:16 ic5buf<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at it s virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.2 ?clr, set, and inv registers? for more informa- tion.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 47 pic32mx330/350/370/430/450/470 table 4-5: output compare 1 throug h output compare 5 register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 oc1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3010 oc1r 31:16 oc1r<31:0> xxxx 15:0 xxxx 3020 oc1rs 31:16 oc1rs<31:0> xxxx 15:0 xxxx 3200 oc2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3210 oc2r 31:16 oc2r<31:0> xxxx 15:0 xxxx 3220 oc2rs 31:16 oc2rs<31:0> xxxx 15:0 xxxx 3400 oc3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3410 oc3r 31:16 oc3r<31:0> xxxx 15:0 xxxx 3420 oc3rs 31:16 15:0 oc3rs<31:0> xxxx xxxx 3600 oc4con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3610 oc4r 31:16 oc4r<31:0> xxxx 15:0 xxxx 3620 oc4rs 31:16 15:0 oc4rs<31:0> xxxx xxxx 3800 oc5con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? ? ? ? ? ? oc32 ocflt octsel ocm<2:0> 0000 3810 oc5r 31:16 oc5r<31:0> xxxx 15:0 xxxx 3820 oc5rs 31:16 oc5rs<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 48 preliminary ? 2012-2013 microchip technology inc. table 4-6: i2c1 and i2c2 register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5000 i2c1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen bfff 5010 i2c1stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 5020 i2c1add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? address register 0000 5030 i2c1msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? address mask register 0000 5040 i2c1brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5050 i2c1trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5060 i2c1rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 5100 i2c2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl sclrel strict a10m disslw smen gcen stren ackdt acken rcen pen rsen sen bfff 5110 i2c2stat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ackstat trstat ? ? ? bcl gcstat add10 iwcol i2cov d_a p s r_w rbf tbf 0000 5120 i2c2add 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? address register 0000 5130 i2c2msk 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? address mask register 0000 5140 i2c2brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? baud rate generator register 0000 5150 i2c2trn 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? transmit register 0000 5160 i2c2rcv 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? receive register 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except i2cxrcv have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 49 pic32mx330/350/370/430/450/470 table 4-7: uart1 through uart5 register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 u1mode (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidlirenrtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6010 u1sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda ffff 6020 u1txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6030 u1rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6040 u1brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 baud rate generator prescaler 0000 6200 u2mode (1) 31:16 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 on ?sidlirenrtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6210 u2sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda ffff 6220 u2txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6230 u2rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6240 u2brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 baud rate generator prescaler 0000 6400 u3mode (1) 31:16 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 on ?sidlirenrtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6410 u3sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda ffff 6420 u3txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6430 u3rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6440 u3brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 baud rate generator prescaler 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at it s virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.2 ?clr, set, and inv registers? for more informa- tion.
pic32mx330/350/370/430/450/470 ds60001185b-page 50 preliminary ? 2012-2013 microchip technology inc. 6600 u4mode (1) 31:16 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 on ?sidlirenrtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6610 u4sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda ffff 6620 u4txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6630 u4rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6640 u4brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 baud rate generator prescaler 0000 6800 u5mode (1) 31:16 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 on ?sidlirenrtsmd ? uen<1:0> wake lpback abaud rxinv brgh pdsel<1:0> stsel 0000 6810 u5sta (1) 31:16 ? ? ? ? ? ? ? adm_en addr<7:0> 0000 15:0 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt urxisel<1:0> adden ridle perr ferr oerr urxda ffff 6820 u5txreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? tx8 transmit register 0000 6830 u5rxreg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? rx8 receive register 0000 6840 u5brg (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 baud rate generator prescaler 0000 table 4-7: uart1 through uart5 register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at it s virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.2 ?clr, set, and inv registers? for more informa- tion.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 51 pic32mx330/350/370/430/450/470 table 4-8: spi2 and spi2 register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5800 spi1con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> mclksel ? ? ? ? ? spife enhbuf 0000 15:0 on ? sidl dissdo mode32 mode16 smp cke ssen ckp msten dissdi stxisel<1:0> srxisel<1:0> 0000 5810 spi1stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? frmerr spibusy ? ? spitur srmt spirov spirbe ?spitbe ?spitbfspirbf 19eb 5820 spi1buf 31:16 data<31:0> 0000 15:0 0000 5830 spi1brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ?brg<8:0> 0000 5840 spi1con2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 spi sgnext ? ? frm erren spi roven spi turen ignrov igntur auden ? ? ? aud mono ?audmod<1:0> 0000 5a00 spi2con 31:16 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> mclksel ? ? ? ? ? spife enhbuf 0000 15:0 on ? sidl dissdo mode32 mode16 smp cke ssen ckp msten dissdi stxisel<1:0> srxisel<1:0> 0000 5a10 spi2stat 31:16 ? ? ? rxbufelm<4:0> ? ? ? txbufelm<4:0> 0000 15:0 ? ? ? frmerr spibusy ? ? spitur srmt spirov spirbe ?spitbe ?spitbfspirbf 19eb 5a20 spi2buf 31:16 data<31:0> 0000 15:0 0000 5a30 spi2brg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ?brg<8:0> 0000 5a40 spi2con2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 spi sgnext ? ? frm erren spi roven spi turen ignrov igntur auden ? ? ? aud mono ?audmod<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table except spixbuf have corresponding clr, set and inv registers at their virtual addresses, plus offse ts of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 52 preliminary ? 2012-2013 microchip technology inc. table 4-9: adc register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9000 ad1con1 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ?sidl ? ? form<2:0> ssrc<2:0> clrasam ?asamsampdone 0000 9010 ad1con2 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 vcfg<2:0> offcal ? cscna ? ?bufs ?smpi<3:0>bufmalts 0000 9020 ad1con3 (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 adrc ? ? samc<4:0> adcs<7:0> 0000 9040 ad1chs (1) 31:16 ch0nb ? ? ch0sb<4:0> ch0na ? ? ch0sa<4:0> 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 9050 ad1cssl (1) 31:16 ? cssl30 cssl29 cssl28 cssl27 cssl26 cssl25 cssl24 cssl23 cssl22 cssl21 cssl20 cssl19 cssl18 cssl17 cssl16 0000 15:0 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 c ssl8 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 0000 9070 adc1buf0 31:16 adc result word 0 (adc1buf0<31:0>) 0000 15:0 0000 9080 adc1buf1 31:16 adc result word 1 (adc1buf1<31:0>) 0000 15:0 0000 9090 adc1buf2 31:16 adc result word 2 (adc1buf2<31:0>) 0000 15:0 0000 90a0 adc1buf3 31:16 adc result word 3 (adc1buf3<31:0>) 0000 15:0 0000 90b0 adc1buf4 31:16 adc result word 4 (adc1buf4<31:0>) 0000 15:0 0000 90c0 adc1buf5 31:16 adc result word 5 (adc1buf5<31:0>) 0000 15:0 0000 90d0 adc1buf6 31:16 adc result word 6 (adc1buf6<31:0>) 0000 15:0 0000 90e0 adc1buf7 31:16 adc result word 7 (adc1buf7<31:0>) 0000 15:0 0000 90f0 adc1buf8 31:16 adc result word 8 (adc1buf8<31:0>) 0000 15:0 0000 9100 adc1buf9 31:16 adc result word 9 (adc1buf9<31:0>) 0000 15:0 0000 9110 adc1bufa 31:16 adc result word a (adc1bufa<31:0>) 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for details.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 53 pic32mx330/350/370/430/450/470 9120 adc1bufb 31:16 adc result word b (adc1bufb<31:0>) 0000 15:0 0000 9130 adc1bufc 31:16 adc result word c (adc1bufc<31:0>) 0000 15:0 0000 9140 adc1bufd 31:16 adc result word d (adc1bufd<31:0>) 0000 15:0 0000 9150 adc1bufe 31:16 adc result word e (adc1bufe<31:0>) 0000 15:0 0000 9160 adc1buff 31:16 adc result word f (adc1buff<31:0>) 0000 15:0 0000 table 4-9: adc register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for details.
pic32mx330/350/370/430/450/470 ds60001185b-page 54 preliminary ? 2012-2013 microchip technology inc. table 4-10: dma global register map virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 dmacon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? suspend dmabusy ? ? ? ? ? ? ? ? ? ? ? 0000 3010 dmastat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rdwr dmach<2:0> 0000 3020 dmaaddr 31:16 dmaaddr<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv re gisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information. table 4-11: dma crc register map virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3030 dcrccon 31:16 ? ? byto<1:0> wbo ? ? bito ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? plen<4:0> crcen crcapp crctyp ? ? crcch<2:0> 0000 3040 dcrcdata 31:16 dcrcdata<31:0> 0000 15:0 0000 3050 dcrcxor 31:16 dcrcxor<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 55 pic32mx330/350/370/430/450/470 table 4-12: dma channel 0 through channel 3 register map virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3060 dch0con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3070 dch0econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? fff8 3080 dch0int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3090 dch0ssa 31:16 chssa<31:0> 0000 15:0 0000 30a0 dch0dsa 31:16 chdsa<31:0> 0000 15:0 0000 30b0 dch0ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 30c0 dch0dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 30d0 dch0sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 30e0 dch0dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 30f0 dch0csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3100 dch0cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3110 dch0dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 3120 dch1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 3130 dch1econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? fff8 3140 dch1int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3150 dch1ssa 31:16 chssa<31:0> 0000 15:0 0000 3160 dch1dsa 31:16 chdsa<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 56 preliminary ? 2012-2013 microchip technology inc. 3170 dch1ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3180 dch1dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3190 dch1sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 31a0 dch1dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 31b0 dch1csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 31c0 dch1cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 31d0 dch1dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 31e0 dch2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 31f0 dch2econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? fff8 3200 dch2int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 3210 dch2ssa 31:16 chssa<31:0> 0000 15:0 0000 3220 dch2dsa 31:16 chdsa<31:0> 0000 15:0 0000 3230 dch2ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3240 dch2dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3250 dch2sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3260 dch2dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3270 dch2csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 table 4-12: dma channel 0 through channel 3 register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 57 pic32mx330/350/370/430/450/470 3280 dch2cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3290 dch2dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 32a0 dch3con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chbusy ? ? ? ? ? ? chchns chen chaed chchn chaen ? chedet chpri<1:0> 0000 32b0 dch3econ 31:16 ? ? ? ? ? ? ? ? chairq<7:0> 00ff 15:0 chsirq<7:0> cforce cabort paten sirqen airqen ? ? ? fff8 32c0 dch3int 31:16 ? ? ? ? ? ? ? ? chsdie chshie chddie chdhie chbcie chccie chtaie cherie 0000 15:0 ? ? ? ? ? ? ? ? chsdif chshif chddif chdhif chbcif chccif chtaif cherif 0000 32d0 dch3ssa 31:16 chssa<31:0> 0000 15:0 0000 32e0 dch3dsa 31:16 chdsa<31:0> 0000 15:0 0000 32f0 dch3ssiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chssiz<15:0> 0000 3300 dch3dsiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdsiz<15:0> 0000 3310 dch3sptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chsptr<15:0> 0000 3320 dch3dptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chdptr<15:0> 0000 3330 dch3csiz 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcsiz<15:0> 0000 3340 dch3cptr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 chcptr<15:0> 0000 3350 dch3dat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? chpdat<7:0> 0000 table 4-12: dma channel 0 through channel 3 register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 58 preliminary ? 2012-2013 microchip technology inc. table 4-13: comparator register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 a000 cm1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on coe cpol ? ? ? ? cout evpol<1:0> ? cref ? ?cch<1:0> e1c3 a010 cm2con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on coe cpol ? ? ? ? cout evpol<1:0> ? cref ? ?cch<1:0> e1c3 a060 cmstat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ?sidl ? ? ? ? ? ? ? ? ? ? c3out c2out c1out 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information. table 4-14: comparator voltage reference register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9800 cvrcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? ? ? ? ? ? ? cvroe cvrr cvrss cvr<3:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: the register in this table has corresponding clr, set and inv regi sters at their virtual addresses, plus offsets of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 59 pic32mx330/350/370/430/450/470 table 4-15: flash controller register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f400 nvmcon (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 wr wren wrerr lvderr lvdstat ? ? ? ? ? ? ? nvmop<3:0> 0000 f410 nvmkey 31:16 nvmkey<31:0> 0000 15:0 0000 f420 nvmaddr (1) 31:16 nvmaddr<31:0> 0000 15:0 0000 f430 nvmdata 31:16 nvmdata<31:0> 0000 15:0 0000 f440 nvmsrc addr 31:16 nvmsrcaddr<31:0> 0000 15:0 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at their virtual addresses, plus offs ets of 0x4, 0x8 and 0xc, respec tively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 60 preliminary ? 2012-2013 microchip technology inc. table 4-16: system control register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f000 osccon 31:16 ? ? pllodiv<2:0> frcdiv<2:0> ? soscrdy pbdivrdy pbdiv<1:0> pllmult<2:0> x1xx (2) 15:0 ? cosc<2:0> ? nosc<2:0> clklock ulock (4) slock slpen cf ufrcen (4) soscen oswen xxxx (2) f010 osctun 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? tun<5:0> 0000 f020 refocon 31:16 ? rodiv<14:0> 0000 15:0 on ?sidl oe rslp ? divswen active ? ? ? ? rosel<3:0> 0000 f030 refotrim 31:16 rotrim<8:0> ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 0000 wdtcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? ? ? ? ? ? ? ? swdtps<4:0> wdtwinen wdtclr 0000 f600 rcon 31:16 ? ?hvdr ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cmr vregs extr swr ? wdto sleep idle bor por xxxx (2) f610 rswrst 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?swrst 0000 f200 cfgcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ?iolockpmdlock ? ? ? ? ? ? ? ?jtagen troen ? tdoen 000b f230 syskey (3) 31:16 syskey<31:0> 0000 15:0 0000 f240 pmd1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ?cvrmd ? ? ?ctmumd ? ? ? ? ? ? ?ad1md 0000 f250 pmd2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? cmp2md cmp1md 0000 f260 pmd3 31:16 ? ? ? ? ? ? ? ? ? ? ? oc5md oc4md oc3md oc2md oc1md 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ic5md ic4md ic3md ic2md ic1md 0000 f270 pmd4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? t5md t4md t3md t2md t1md 0000 f280 pmd5 31:16 ? ? ? ? ? ? ? usb1md (5) ? ? ? ? ? ? i2c1md i2c1md 0000 15:0 ? ? ? ? ? ? spi2md spi1md ? ? ?u5md (4) u4md u3md u2md u1md 0000 f290 pmd6 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pmpmd 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? refomd rtccmd 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: with the exception of those noted, all registers in this table have corresponding clr, set and inv registers at their virtual a ddresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information. 2: reset values are dependent on the devcfgx configuration bits and the type of reset. 3: this register does not have associated clr, set, inv registers. 4: this bit is available on 100-pin devices only. 5: this bit is available on pic32mx4xx devices only.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 61 pic32mx330/350/370/430/450/470 table 4-17: devcfg: device co nfiguration word summary virtual address (bfc0_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2ff0 devcfg3 31:16 fvbusonio fusbidio iol1way pmdl1way ? ? ? ? ? ? ? ? ? fsrssel<2:0> xxxx 15:0 userid<15:0> xxxx 2ff4 devcfg2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? fpllodiv<2:0> xxxx 15:0 upllen (1) ? ? ? ? upllidiv<2:0> (1) ?fpllmul<2:0> ? fpllidiv<2:0> xxxx 2ff8 devcfg1 31:16 ? ? ? ? ? ? fwdtwinsz<1:0> fwdten windis ? wdtps<4:0> xxxx 15:0 fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmod<1:0> ieso ? fsoscen ? ?fnosc<2:0> xxxx 2ffc devcfg0 31:16 ? ? ?cp ? ? ?bwp ? ? ? ?pwp<7:4> xxxx 15:0 pwp<3:0> ? ? ? ? ? ? ? icesel<1:0> jtagen debug<1:0> xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this bit is available on pic32mx4xx devices only. table 4-18: device and revision id summary virtual address (bf80_#) register name bit range bits all resets (1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 f220 devid 31:16 ver<3:0> devid<27:16> xxxx 15:0 devid<15:0> xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: reset values are dependent on the device variant.
pic32mx330/350/370/430/450/470 ds60001185b-page 62 preliminary ? 2012-2013 microchip technology inc. table 4-19: porta register map for pic32mx330f064l, pic32mx350f128l, pic32mx350f256l, pic32mx370f512l, pic32mx430f064l, pic32mx450f128l, pic32mx4 50f256l, and pic32mx4 70f512l devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 ansela 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ansela10 ansela9 ? ? ? ? ? ? ? ? ? 0060 6010 trisa 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisa15 trisa14 ? ? ? trisa10 trisa9 ? trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 xxxx 6020 porta 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ra15 ra14 ? ? ? ra10 ra9 ? ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 xxxx 6030 lata 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 lata15 lata14 ? ? ? lata10 lata9 ? lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 xxxx 6040 odca 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odca15 odca14 ? ? ? ? ? ? odca7 odca6 odca5 odca4 odca3 odca2 odca1 odca0 xxxx 6050 cnpua 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpua15 cnpua14 ? ? ? cnpua10 cnpua9 ? cnpua7 cnpua6 cnpua5 cnpua4 cnpua3 cnpua2 cnpua1 cnpua0 xxxx 6060 cnpda 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpda15 cnpda14 ? ? ? cnpda10 cnpda9 ? cnpda7 cnpda6 cnpda5 cnpda4 cnpda3 cnpda2 cnpda1 cnpda0 xxxx 6070 cncona 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6080 cnena 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cniea15 cniea14 ? ? ? cniea10 cniea9 ? cniea7 cniea6 cniea5 cniea4 cniea3 cniea2 cniea1 cniea0 xxxx 6090 cnstata 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cn stata15 cn stata14 ? ? ? cn stata10 cn stata9 ? cn stata7 cn stata6 cn stata5 cn stata4 cn stata3 cn stata2 cn stata1 cn stata0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 63 pic32mx330/350/370/430/450/470 table 4-20: portb register map virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 anselb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 anselb15 anselb14 anselb13 anselb12 anselb11 anselb10 anselb9 anselb8 anselb7 anselb6 anselb5 anselb4 anselb3 anselb2 anselb1 anselb0 ffff 6110 trisb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisb15 trisb14 trisb13 trisb12 trisb11 trisb10 trisb9 trisb8 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 xxxx 6120 portb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rb15 rb14 rb13 rb12 rb11 rb10 rb9 rb8 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx 6130 latb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latb15 latb14 latb13 latb12 latb11 latb10 latb9 latb8 latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx 6150 cnpub 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpub15 cnpub14 cnpub13 cnpub12 cnpub11 cnpub10 cnpub9 cnpub8 cnpub7 cnpub6 cnpub5 cnpub4 cnpub3 cnpub2 cnpub1 cnpub0 xxxx 6160 cnpdb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpdb15 cnpdb14 cnpdb13 cnpdb12 cnpdb11 cnpdb10 cnpdb9 cnpdb8 cnpdb7 cnpdb6 cnpdb5 cnpdb4 cnpdb3 cnpdb2 cnpdb1 cnpdb0 xxxx 6170 cnconb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6180 cnenb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnieb15 cnieb14 cnieb13 cnieb12 cnieb11 cnieb10 cnieb9 cnieb8 cnieb7 cnieb6 cnieb5 cnieb4 cnieb3 cnieb2 cnieb1 cnieb0 xxxx 6190 cnstatb 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cn statb15 cn statb14 cn statb13 cn statb12 cn statb11 cn statb10 cn statb9 cn statb8 cn statb7 cn statb6 cn statb5 cn statb4 cn statb3 cn statb2 cn statb1 cn statb0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv re gisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 64 preliminary ? 2012-2013 microchip technology inc. table 4-21: portc register map for pic32mx330f064l, pic32mx350f128l, pic32mx350f256l, pic32mx370f512l, pic32mx430f064l, pic32mx450f128l, pic32mx4 50f256l, and pic32mx470 f512l devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6200 anselc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? f000 6210 trisc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisc15 trisc14 trisc13 trisc12 ? ? ? ? ? ? ? trisc4 trisc3 trisc2 trisc1 ? xxxx 6220 portc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rc15 rc14 rc13 rc12 ? ? ? ? ? ? ? rc4 rc3 rc2 rc1 ? xxxx 6230 latc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latc15 latc14 latc13 latc12 ? ? ? ? ? ? ? latc4 latc3 latc2 latc1 ? xxxx 6240 odcc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? odcc4 odcc3 odcc2 odcc1 ? xxxx 6250 cnpuc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpuc15 cnpuc14 cnpuc13 cnpuc12 ? ? ? ? ? ? ? cnpuc4 cnpuc3 cnpuc2 cnpuc1 ? xxxx 6260 cnpdc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpdc15 cnpdc14 cnpdc13 cnpdc12 ? ? ? ? ? ? ? cnpdc4 cnpdc3 cnpdc2 cnpdc1 ? xxxx 6270 cnconc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6280 cnenc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cniec15 cniec14 cniec13 cniec12 ? ? ? ? ? ? ? cniec4 cniec3 cniec2 cniec1 ? xxxx 6290 cnstatc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnstatc15 cnstatc14 cnstatc13 cnstatc12 ? ? ? ? ? ? ? cnstatc4 cnstatc3 cnstatc2 cnstatc1 ? xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 65 pic32mx330/350/370/430/450/470 table 4-22: portc register map for pic32mx330f064h, pic32mx350f128h, pic32mx350f256h, pic32mx370f512h, pic32mx430f064h, pic32mx450f128h, pic32mx4 50f256h, and pic32mx 470f512h devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6210 trisc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisc15 trisc14 trisc13 trisc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx 6220 portc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rc15 rc14 rc13 rc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx 6230 latc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latc15 latc14 latc13 latc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx 6250 cnpuc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpuc15 cnpuc14 cnpuc13 cnpuc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx 6260 cnpdc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpdc15 cnpdc14 cnpdc13 cnpdc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx 6270 cnconc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6280 cnenc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cniec15 cniec14 cniec13 cniec12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx 6290 cnstatc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnstatc15 cnstatc14 cnstatc13 cnstatc12 ? ? ? ? ? ? ? ? ? ? ? ? xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 66 preliminary ? 2012-2013 microchip technology inc. table 4-23: portd register map for pic32mx330f064l, pic32mx350f128l, pic32mx350f256l, pic32mx370f512l, pic32mx430f064l, pic32mx450f128l, pic32mx4 50f256l, and pic32mx4 70f512l devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6300 anseld 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? anseld3 anseld2 anseld1 ? 00e0 6310 trisd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisd15 trisd14 trisd13 trisd12 trisd11 trisd10 trisd9 trisd8 trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 xxxx 5320 portd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx 6330 latd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latd15 latd14 latd13 latd12 latd11 latd10 latd9 latd8 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx 6340 odcd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcd15 odcd14 odcd13 odcd12 odcd11 odcd10 odcd9 odcd8 odcd7 odcd6 odcd5 odcd4 ? ? ? odcd0 xxxx 6350 cnpud 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpud15 cnpud14 cnpud13 cnpud12 cnpud11 cnpud10 cnpud9 cnpud8 cnpud7 cnpud6 cnpud5 cnpud4 cnpud3 cnpud2 cnpud1 cnpud0 xxxx 6360 cnpdd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpdd15 cnpdd14 cnpdd13 cnpdd12 cnpdd11 cnpdd10 cnpdd9 cnpdd8 cnpdd7 cnpdd6 cnpdd5 cnpdd4 cnpdd3 cnpdd2 cnpdd1 cnpdd0 xxxx 6370 cncond 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6380 cnend 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnied15 cnied14 cnied13 cnied12 cnied11 cnied10 cnied9 cnied8 cnied7 cnied6 cnied5 cnied4 cnied3 cnied2 cnied1 cnied0 xxxx 6390 cnstatd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cns tatd15 cn statd14 cn statd13 cn statd12 cn statd11 cn statd10 cn statd9 cn statd8 cn statd7 cn statd6 cn statd5 cn statd4 cn statd3 cn statd2 cn statd1 cn statd0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 67 pic32mx330/350/370/430/450/470 table 4-24: portd register map for pic32mx330f064h, pic32mx350f128h, pic32mx350f256h, pic32mx370f512h, pic32mx430f064h, pic32mx450f128h, pic32m x450f256h, PIC32MX470F512H devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6300 anseld 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? anseld3 anseld2 anseld1 ? 00e0 6310 trisd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? trisd11 trisd10 trisd9 trisd8 trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 xxxx 5320 portd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? rd11 rd10 rd9 rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx 6330 latd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? latd11 latd10 latd9 latd8 latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 xxxx 6340 odcd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? odcd11 odcd10 odcd9 odcd8 odcd7 odcd6 odcd5 odcd4 ? ? ? odcd0 xxxx 6350 cnpud 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? cnpud11 cnpud10 cnpud9 cnpud8 cnpud7 cnpud6 cnpud5 cnpud4 cnpud3 cnpud2 cnpud1 cnpud0 xxxx 6360 cnpdd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? cnpdd11 cnpdd10 cnpdd9 cnpdd8 cnpdd7 cnpdd6 cnpdd5 cnpdd4 cnpdd3 cnpdd2 cnpdd1 cnpdd0 xxxx 6370 cncond 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6380 cnend 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? cnied11 cnied10 cnied9 cnied8 cnied7 cnied6 cnied5 cnied4 cnied3 cnied2 cnied1 cnied0 xxxx 6390 cnstatd 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? cn statd11 cn statd10 cn statd9 cn statd8 cn statd7 cn statd6 cn statd5 cn statd4 cn statd3 cn statd2 cn statd1 cn statd0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 68 preliminary ? 2012-2013 microchip technology inc. table 4-25: porte register map fo r pic32mx330f064l, pic32mx350f128l, pic32mx350f256l, pic32mx370f512l, pic32mx430f064l, pic32mx450f128l, pic3 2mx450f256l, pic32mx470f512l devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6400 ansele 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ansele7 ansele6 ansele5 ansele4 ? ansele2 ? ? 00f4 6410 trise 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? trise9 trise8 trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 xxxx 6420 porte 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? re9 re8 re7 re6 re5 re4 re3 re2 re1 re0 xxxx 6440 late 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? late9 late8 late7 late6 late5 late4 late3 late2 late1 late0 xxxx 6440 odce 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? odce9 odce8 ? ? ? ? odce3 ? odce1 odce0 xxxx 6450 cnpue 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cnpue9 cnpue8 cnpue7 cnpue6 cnpue5 cnpue4 cnpde3 cnpue2 cnpue1 cnpue0 xxxx 6460 cnpde 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cnpde9 cnpde8 cnpde7 cnpde6 cnpde5 cnpde4 cnpde3 cnpde2 cnpde1 cnpde0 xxxx 6470 cncone 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6480 cnene 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cniee9 cniee8 cniee7 cniee6 cniee5 cniee4 cniee3 cniee2 cniee1 cniee0 xxxx 6490 cnstate 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cn state9 cn state8 cn state7 cn state6 cn state5 cn state4 cn state3 cn state2 cn state1 cn state0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 69 pic32mx330/350/370/430/450/470 table 4-26: porte register map for pic32mx330f064h, pic32mx350f128h, pic32mx350f256h, pic32mx370f512h, pic32mx430f064h, pic32mx450f128h, pic32mx4 50f256h, and pic32mx 470f512h devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6400 ansele 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ansele7 ansele6 ansele5 ansele4 ? ansele2 ? ? 00f4 6410 trise 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 xxxx 6420 porte 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? re7 re6 re5 re4 re3 re2 re1 re0 xxxx 6440 late 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? late7 late6 late5 late4 late3 late2 late1 late0 xxxx 6440 odce 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? odce3 ? odce1 odce0 xxxx 6450 cnpue 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? cnpue7 cnpue6 cnpue5 cnpue4 cnpde3 cnpue2 cnpue1 cnpue0 xxxx 6460 cnpde 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? cnpde7 cnpde6 cnpde5 cnpde4 cnpde3 cnpde2 cnpde1 cnpde0 xxxx 6470 cncone 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6480 cnene 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? cniee7 cniee6 cniee5 cniee4 cniee3 cniee2 cniee1 cniee0 xxxx 6490 cnstate 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? cn state7 cn state6 cn state5 cn state4 cn state3 cn state2 cn state1 cn state0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 70 preliminary ? 2012-2013 microchip technology inc. table 4-27: portf register ma p for pic32mx330f064l, pic32mx350f128l, pic32mx350f2 56l, and pic32mx370f512l devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6510 trisf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? trisf13 trisf12 ? ? ? trisf8 trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 xxxx 6520 portf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? rf13 rf12 ? ? ? rf8 rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 xxxx 6530 latf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? latf13 latf12 ? ? ? latf8 latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 xxxx 6540 odcf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? odcf13 odcf12 ? ? ? odcf8 odcf7 odcf6 odcf5 odcf4 odcf3 odcf2 odcf1 odcf0 xxxx 6550 cnpuf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? cnpuf13 cnpuf12 ? ? ? cnpuf8 cnpuf7 cnpuf6 cnpuf5 cnpuf4 cnpdf3 cnpuf2 cnpuf1 cnpuf0 xxxx 6560 cnpdf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? cnpdf13 cnpdf12 ? ? ? cnpdf8 cnpdf7 cnpdf6 cnpdf5 cnpdf4 cnpdf3 cnpdf2 cnpdf1 cnpdf0 xxxx 6570 cnconf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6580 cnenf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? cnief13 cnief12 ? ? ? cnief8 cnief7 cnief6 cnief5 cnief4 cnief3 cnief2 cnief1 cnief0 xxxx 6590 cnstatf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? cn statf13 cn statf12 ? ? ? cn statf8 cn statf7 cn statf6 cn statf5 cn statf4 cn statf3 cn statf2 cn statf1 cn statf0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 71 pic32mx330/350/370/430/450/470 table 4-28: portf register ma p for pic32mx430f064l, pic32m x450f128l, pic32mx450f256l, and pic32mx470f512l devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6510 trisf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? trisf13 trisf12 ? ? ? trisf8 ? ? trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 xxxx 6520 portf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? rf13 rf12 ? ? ? rf8 ? ? rf5 rf4 rf3 rf2 rf1 rf0 xxxx 6530 latf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? latf13 latf12 ? ? ? latf8 ? ? latf5 latf4 latf3 latf2 latf1 latf0 xxxx 6540 odcf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? odcf13 odcf12 ? ? ? odcf8 ? ? odcf5 odcf4 odcf3 odcf2 odcf1 odcf0 xxxx 6550 cnpuf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? cnpuf13 cnpuf12 ? ? ? cnpuf8 ? ? cnpuf5 cnpuf4 cnpdf3 cnpuf2 cnpuf1 cnpuf0 xxxx 6560 cnpdf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? cnpdf13 cnpdf12 ? ? ? cnpdf8 ? ? cnpdf5 cnpff4 cnpdf3 cnpdf2 cnpdf1 cnpdf0 xxxx 6570 cnconf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6580 cnenf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? cnief13 cnief12 ? ? ? cnief8 ? ? cnief5 cnief4 cnief3 cnief2 cnief1 cnief0 xxxx 6590 cnstatf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? cn statf13 cn statf12 ? ? ? cn statf8 ? ? cn statf5 cn statf4 cn statf3 cn statf2 cn statf1 cn statf0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 72 preliminary ? 2012-2013 microchip technology inc. table 4-29: portf register map for pi c32mx330f064h, pic32mx350f1 28h, pic32mx350f256h, and pic32mx370f512h devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6510 trisf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 xxxx 6520 portf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? rf6 rf5 rf4 rf3 rf2 rf1 rf0 xxxx 6530 latf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? latf6 latf5 latf4 latf3 latf2 latf1 latf0 xxxx 6540 odcf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? odcf6 odcf5 odcf4 odcf3 odcf2 odcf1 odcf0 xxxx 6550 cnpuf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? cnpuf6 cnpuf5 cnpuf4 cnpuf3 cnpuf2 cnpuf1 cnpuf0 xxxx 6560 cnpdf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? cnpdf6 cnpdf5 cnpdf4 cnpdf3 cnpdf2 cnpdf1 cnpdf0 xxxx 6570 cnconf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6580 cnenf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? cnief6 cnief5 cnief4 cnief3 cnief2 cnief1 cnief0 xxxx 6590 cnstatf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? cn statf6 cn statf5 cn statf4 cn statf3 cn statf2 cn statf1 cn statf0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 73 pic32mx330/350/370/430/450/470 table 4-30: portf register map for pi c32mx430f064h, pic32mx450f1 28h, pic32mx450f256h, and PIC32MX470F512H devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6510 trisf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? trisf5 trisf4 trisf3 ? trisf1 trisf0 xxxx 6520 portf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? rf5 rf4 rf3 ? rf1 rf0 xxxx 6530 latf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? latf5 latf4 latf3 ? latf1 latf0 xxxx 6540 odcf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? odcf5 odcf4 odcf3 ? odcf1 odcf0 xxxx 6550 cnpuf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? cnpuf5 cnpuf4 cnpuf3 ? cnpuf1 cnpuf0 xxxx 6560 cnpdf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? cnpdf5 cnpdf4 cnpdf3 ? cnpdf1 cnpdf0 xxxx 6570 cnconf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6580 cnenf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? cnief5 cnief4 cnief3 ? cnief1 cnief0 xxxx 6590 cnstatf 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? cn statf5 cn statf4 cn statf3 ? cn statf1 cn statf0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 74 preliminary ? 2012-2013 microchip technology inc. table 4-31: portg register map for pic32mx330f064l, pic32mx350f128l, pic32mx350f256l, pic32mx370f512l, pic32mx430f064l, pic32mx450f128l, pic32mx4 50f256l, and pic32mx4 70f512l devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6600 anselg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? anselg9 anselg8 anselg7 anselg6 ? ? ? ? ? ? 01c0 6610 trisg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 trisg15 trisg14 trisg13 trisg12 ? ? trisg9 trisg8 trisg7 trisg6 ? ? trisg3 trisg2 trisg1 trisg0 xxxx 6620 portg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 rg15 rg14 rg13 rg12 ? ? rg9 rg8 rg7 rg6 ? ? rg3 rg2 rg1 rg0 xxxx 6630 latg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 latg15 latg14 latg13 latg12 ? ? latg9 latg8 latg7 latg6 ? ? latg3 latg2 latg1 latg0 xxxx 6640 odcg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 odcg15 odcg14 odcg13 odcg12 ? ? ? ? ? ? ? ? odcg3 odcg2 odcg1 odcg0 xxxx 6650 cnpug 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpug15 cnpug14 cnpug13 cnpug12 ? ? cnpug9 cnpug8 cnpug7 cnpug6 ? ? cnpug3 cnpug2 cnpug1 cnpug0 xxxx 6660 cnpdg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnpdg15 cnpdg14 cnpdg13 cnpdg12 ? ? cnpdg9 cnpdg8 cnpdg7 cnpdg6 ? ? cnpdg3 cnpdg2 cnpdg1 cnpdg0 xxxx 6670 cncong 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6680 cneng 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cnieg15 cnieg14 cnieg13 cnieg12 ? ? cnieg9 cnieg8 cnieg7 cnieg6 ? ? cnieg3 cnieg2 cnieg1 cnieg0 xxxx 6690 cnstatg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cn statg15 cn statg14 cn statg13 cn statg12 ? ? cn statg9 cn statg8 cn statg7 cn statg6 ? ? cn statg3 cn statg2 cn statg1 cn statg0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 75 pic32mx330/350/370/430/450/470 table 4-32: portg register map fo r pic32mx330f064h, pic32mx350f128h, pic32mx350f256h, pic32mx370f512h, pic32mx430f064h, pic32mx450f128h, pic32mx4 50f256h, and pic32mx 470f512h devices only virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6600 anselg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? anselg9 anselg8 anselg7 anselg6 ? ? ? ? ? ? 01c0 6610 trisg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? trisg9 trisg8 trisg7 trisg6 ? ? trisg3 trisg2 trisg1 trisg0 xxxx 6620 portg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? rg9 rg8 rg7 rg6 ? ? rg3 rg2 rg1 rg0 xxxx 6630 latg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? latg9 latg8 latg7 latg6 ? ? latg3 latg2 latg1 latg0 xxxx 6640 odcg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? odcg3 odcg2 odcg1 odcg02 xxxx 6650 cnpug 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cnpug9 cnpug8 cnpug7 cnpug6 ? ? cnpug3 cnpug2 cnpug1 cnpug0 xxxx 6660 cnpdg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cnpdg9 cnpdg8 cnpdg7 cnpdg6 ? ? cnpdg3 cnpdg2 cnpdg1 cnpdg0 xxxx 6670 cncong 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 6680 cneng 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cnieg9 cnieg8 cnieg7 cnieg6 ? ? cnieg3 cnieg2 cnieg1 cnieg0 xxxx 6690 cnstatg 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? cn statg9 cn statg8 cn statg7 cn statg6 ? ? cn statg3 cn statg2 cn statg1 cn statg0 xxxx legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?; reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv r egisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 76 preliminary ? 2012-2013 microchip technology inc. table 4-33: peripheral pin select input register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 fa04 int1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?int1r<3:0> 0000 fa08 int2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?int2r<3:0> 0000 fa0c int3r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?int3r<3:0> 0000 fa10 int4r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?int4r<3:0> 0000 fa18 t2ckr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?t2ckr<3:0> 0000 fa1c t3ckr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?t3ckr<3:0> 0000 fa20 t4ckr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?t4ckr<3:0> 0000 fa24 t5ckr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?t5ckr<3:0> 0000 fa28 ic1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ic1r<3:0> 0000 fa2c ic2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ic2r<3:0> 0000 fa30 ic3r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ic3r<3:0> 0000 fa34 ic4r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ic4r<3:0> 0000 fa38 ic5r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ic5r<3:0> 0000 fa48 ocfar 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ocfar<3:0> 0000 fa4c ocfbr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?ocfbr<3:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 77 pic32mx330/350/370/430/450/470 fa50 u1rxr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?u1rxr<3:0> 0000 fa54 u1ctsr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? u1ctsr<3:0> 0000 fa58 u2rxr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?u2rxr<3:0> 0000 fa5c u2ctsr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? u2ctsr<3:0> 0000 fa60 u3rxr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?u3rxr<3:0> 0000 fa64 u3ctsr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? u3ctsr<3:0> 0000 fa68 u4rxr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?u4rxr<3:0> 0000 fa6c u4ctsr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? u4ctsr<3:0> 0000 fa70 u5rxr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?u5rxr<3:0> 0000 fa74 u5ctsr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? u5ctsr<3:0> 0000 fa84 sdi1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?sdi1r<3:0> 0000 fa88 ss1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ss1r<3:0> 0000 fa90 sdi2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?sdi2r<3:0> 0000 fa94 ss2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ss2r<3:0> 0000 fad0 refclkir 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? refclkir<3:0> 0000 table 4-33: peripheral pin select input register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal.
pic32mx330/350/370/430/450/470 ds60001185b-page 78 preliminary ? 2012-2013 microchip technology inc. table 4-34: peripheral pin select output register map virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 fb38 rpa14r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?rpa14<3:0> 0000 fb3c rpa15r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?rpa15<3:0> 0000 fb40 rpb0r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb0<3:0> 0000 fb44 rpb1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb1<3:0> 0000 fb48 rpb2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb2<3:0> 0000 fb4c rpb3r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb3<3:0> 0000 fb54 rpb5r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb5<3:0> 0000 fb58 rpb6r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb6<3:0> 0000 fb5c rpb7r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb7<3:0> 0000 fb60 rpb8r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb8<3:0> 0000 fb64 rpb9r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb9<3:0> 0000 fb68 rpb10r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb10<3:0> 0000 fb78 rpb14r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb14<3:0> 0000 fb7c rpb15r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpb15<3:0> 0000 fb84 rpc1r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc1<3:0> 0000 fb88 rpc2r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc2<3:0> 0000 fb8c rpc3r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc3<3:0> 0000 fb90 rpc4r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc4<3:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register is not available on 64-pin devices.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 79 pic32mx330/350/370/430/450/470 fbb4 rpc13r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc13<3:0> 0000 fbb8 rpc14r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpc14<3:0> 0000 fbc0 rpd0r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd0<3:0> 0000 fbc4 rpd1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd1<3:0> 0000 fbc8 rpd2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd2<3:0> 0000 fbcc rpd3r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd3<3:0> 0000 fbd0 rpd4r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd4<3:0> 0000 fbd4 rpd5r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd5<3:0> 0000 fbe0 rpd8r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd8<3:0> 0000 fbe4 rpd9r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd9<3:0> 0000 fbe8 rpd10r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd10<3:0> 0000 fbec rpd11r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?rpd11<3:0> 0000 fbf0 rpd12r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd12<3:0> 0000 fbf8 rpd14r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd14<3:0> 0000 fbfc rpd15r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpd15<3:0> 0000 fc0c rpe3r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpe3<3:0> 0000 fc14 rpe5r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpe5<3:0> 0000 fc20 rpe8r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpe8<3:0> 0000 table 4-34: peripheral pin select ou tput register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register is not available on 64-pin devices.
pic32mx330/350/370/430/450/470 ds60001185b-page 80 preliminary ? 2012-2013 microchip technology inc. fc24 rpe9r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpe9<3:0> 0000 fc40 rpf0r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpf0<3:0> 0000 fc44 rpf1r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpf1<3:0> 0000 fc48 rpf2r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpf2<3:0> 0000 fc4c rpf3r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpf3<3:0> 0000 fc50 rpf4r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpf4<3:0> 0000 fc54 rpf5r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpf5<3:0> 0000 fc58 rpf6r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpf6<3:0> 0000 fc5c rpf7r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpf7<3:0> 0000 fc60 rpf8r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpf8<3:0> 0000 fc70 rpf12r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?rpf12<3:0> 0000 fc74 rpf13r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ?rpf13<3:0> 0000 fc80 rpg0r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpg0<3:0> 0000 fc84 rpg1r (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpg1<3:0> 0000 fc98 rpg6r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpg6<3:0> 0000 fc9c rpg7r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpg7<3:0> 0000 fca0 rpg8r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpg8<3:0> 0000 fca4 rpg9r 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? rpg9<3:0> 0000 table 4-34: peripheral pin select ou tput register map (continued) virtual address (bf80_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register is not available on 64-pin devices.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 81 pic32mx330/350/370/430/450/470 table 4-35: parallel mast er port register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 7000 pmcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 on ? sidl adrmux<1:0> pmpttl ptwren ptrden csf<1:0> alp cs2p cs1p ? wrsp rdsp 0000 7010 pmmode 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 busy irqm<1:0> incm<1:0> mode16 mode<1:0> waitb<1:0> waitm<3:0> waite<1:0> 0000 7020 pmaddr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 cs2 cs1 addr<13:0> 0000 7030 pmdout 31:16 dataout<31:0> 0000 15:0 0000 7040 pmdin 31:16 datain<31:0> 0000 15:0 0000 7050 pmaen 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 pten<15:0> 0000 7060 pmstat 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ibf ibov ? ? ib3f ib2f ib1f ib0f obe obuf ? ? ob3eob2eob1eob0e bfbf legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv re gisters at their virtual addresses, plus offsets of 0x4, 0x8 and 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 82 preliminary ? 2012-2013 microchip technology inc. table 4-36: prefetch register map virtual address (bf88_#) register name bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 4000 checon (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? checoh 0000 15:0 ? ? ? ? ? ? dcsz<1:0> ? ? prefen<1:0> ?pfmws<2:0> 0007 4010 cheacc (1) 31:16 chewen ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? cheidx<3:0> 00xx 4020 chetag (1) 31:16 ltagboot ? ? ? ? ? ? ? ltag<23:16> xxx0 15:0 ltag<15:4> lvalid llock ltype ? xxx2 4030 chemsk (1) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 lmask<15:5> ? ? ? ? ? xxxx 4040 chew0 31:16 chew0<31:0> xxxx 15:0 xxxx 4050 chew1 31:16 chew1<31:0> xxxx 15:0 xxxx 4060 chew2 31:16 chew2<31:0> xxxx 15:0 xxxx 4070 chew3 31:16 chew3<31:0> xxxx 15:0 xxxx 4080 chelru 31:16 ? ? ? ? ? ? ? chelru<24:16> 0000 15:0 chelru<15:0> 0000 4090 chehit 31:16 chehit<31:0> xxxx 15:0 xxxx 40a0 chemis 31:16 chemis<31:0> xxxx 15:0 xxxx 40c0 chepfabt 31:16 chepfabt<31:0> xxxx 15:0 xxxx legend: x = unknown value on reset, ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: this register has corresponding clr, set and inv registers at it s virtual address, plus an offset of 0x4, 0x8 and 0xc, respecti vely. see section 12.2 ?clr, set, and inv registers? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 83 pic32mx330/350/370/430/450/470 table 4-37: rtcc register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0200 rtccon 31:16 ? ? ? ? ? ? cal<9:0> 0000 15:0 on ?sidl ? ? ? ? ? rtsecsel rtcclkon ? ? rtcwren rtcsync halfsec rtcoe 0000 0210 rtcalrm 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 alrmen chime piv alrmsync amask<3:0> arpt<7:0> 0000 0220 rtctime 31:16 hr10<3:0> hr01<3:0> min10<3:0> min01<3:0> xxxx 15:0 sec10<3:0> sec01<3:0> ? ? ? ? ? ? ? ? xx00 0230 rtcdate 31:16 year10<3:0> year01<3:0> month10<3:0> month01<3:0> xxxx 15:0 day10<3:0> day01<3:0> ? ? ? ? wday01<3:0> xx00 0240 alrmtime 31:16 hr10<3:0> hr01<3:0> min10<3:0> min01<3:0> xxxx 15:0 sec10<3:0> sec01<3:0> ? ? ? ? ? ? ? ? xx00 0250 alrmdate 31:16 ? ? ? ? ? ? ? ? month10<3:0> month01<3:0> 00xx 15:0 day10<3:0> day01<3:0> ? ? ? ? wday01<3:0> xx0x legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv re gisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information. table 4-38: ctmu register map virtual address (bf80_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 a200 ctmucon 31:16 edg1mod edg1pol edg1sel<3:0> edg2stat edg1stat edg2mod edg2pol edg2sel<3:0> ? ? 0000 15:0 on ? ctmusidl tgen edgen edgseqen idissen cttrig itrim<5:0> irng<1:0> 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: all registers in this table have corresponding clr, set and inv re gisters at its virtual address, plus an offset of 0x4, 0x8 an d 0xc, respectively. see section 12.2 ?clr, set, and inv registers? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 84 preliminary ? 2012-2013 microchip technology inc. table 4-39: usb register map virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5040 u1otgir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif 0000 5050 u1otgie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie 0000 5060 u1otgstat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?id ?lstate ? sesvd sesend ? vbusvd 0000 5070 u1otgcon 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis 0000 5080 u1pwrc 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?uactpnd (4) ? ? uslpgrd usbbusy ? ususpend usbpwr 0000 5200 u1ir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? stallif attachif resumeif idleif trnif sofif uerrif urstif 0000 detachif 0000 5210 u1ie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? stallie attachie resumeie idleie trnie sofie uerrie urstie 0000 detachie 0000 5220 u1eir (2) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? btsef bmxef dmaef btoef dfn8ef crc16ef crc5ef pidef 0000 eofef 0000 5230 u1eie 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? btsee bmxee dmaee btoee dfn8ee crc16ee crc5ee pidee 0000 eofee 0000 5240 u1stat (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? endpt<3:0> dir ppbi ? ? 0000 5250 u1con 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? jstate se0 pktdis usbrst hosten resume ppbrst usben 0000 tokbusy sofen 0000 5260 u1addr 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? lspden devaddr<6:0> 0000 5270 u1bdtp1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptrl<7:1> ? 0000 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: with the exception of those noted, all registers in this table (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc respectively. see section 12.2 ?clr, set, and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associ ated clr, set and inv registers. 4: reset value for this bit is undefined.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 85 pic32mx330/350/370/430/450/470 5280 u1frml (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? frml<7:0> 0000 5290 u1frmh (3) 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? ? ? frmh<2:0> 0000 52a0 u1tok 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? pid<3:0> ep<3:0> 0000 52b0 u1sof 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ?cnt<7:0> 0000 52c0 u1bdtp2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptrh<7:0> 0000 52d0 u1bdtp3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? bdtptru<7:0> 0000 52e0 u1cnfg1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? uteye uoemon ? usbsidl ? ? ? uasuspnd 0000 5300 u1ep0 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? lspd retrydis ? epcondis eprxen eptxen epstall ephshk 0000 5310 u1ep1 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5320 u1ep2 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5330 u1ep3 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5340 u1ep4 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5350 u1ep5 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5360 u1ep6 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5370 u1ep7 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 5380 u1ep8 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 table 4-39: usb register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: with the exception of those noted, all registers in this table (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc respectively. see section 12.2 ?clr, set, and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associ ated clr, set and inv registers. 4: reset value for this bit is undefined.
pic32mx330/350/370/430/450/470 ds60001185b-page 86 preliminary ? 2012-2013 microchip technology inc. 5390 u1ep9 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53a0 u1ep10 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53b0 u1ep11 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53c0 u1ep12 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53d0 u1ep13 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53e0 u1ep14 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 53f0 u1ep15 31:16 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0000 15:0 ? ? ? ? ? ? ? ? ? ? ? epcondis eprxen eptxen epstall ephshk 0000 table 4-39: usb register map (continued) virtual address (bf88_#) register name (1) bit range bits all resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 legend: x = unknown value on reset; ? = unimplemented, read as ? 0 ?. reset values are shown in hexadecimal. note 1: with the exception of those noted, all registers in this table (except as noted) have corresponding clr, set and inv registers at its virtual address, plus an offset of 0x4, 0x8 and 0xc respectively. see section 12.2 ?clr, set, and inv registers? for more information. 2: this register does not have associated set and inv registers. 3: this register does not have associ ated clr, set and inv registers. 4: reset value for this bit is undefined.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 87 pic32mx330/350/370/430/450/470 4.3 control registers register 4-1 through register 4-8 are used for setting the ram and flash memory partitions for data and code. register 4-1: bmxcon: bus matr ix configuration register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 r/w-1 u-0 u-0 ? ? ? ? ? bmx chedma ? ? 23:16 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? bmx errixi bmx erricd bmx errdma bmx errds bmx erris 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 r/w-1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-1 ? bmx wsdrm ? ? ? bmxarb<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared bit 31-27 unimplemented: read as ? 0 ? bit 26 bmxchedma: bmx pfm cacheability for dma accesses bit 1 = enable program flash memory (data) cacheability for dma accesses ? (requires cache to have data caching enabled) 0 = disable program flash memory (data) cacheability for dma accesses ? (hits are still read from the cache, but misses do not update the cache) bit 25-21 unimplemented: read as ? 0 ? bit 20 bmxerrixi: enable bus error from ixi bit 1 = enable bus error exceptions for unmapped address accesses initiated from ixi shared bus 0 = disable bus error exceptions for unmapped address accesses initiated from ixi shared bus bit 19 bmxerricd: enable bus error from icd debug unit bit 1 = enable bus error exceptions for unmapped address accesses initiated from icd 0 = disable bus error exceptions for unmapped address accesses initiated from icd bit 18 bmxerrdma: bus error from dma bit 1 = enable bus error exceptions for unmapped address accesses initiated from dma 0 = disable bus error exceptions for unmapped address accesses initiated from dma bit 17 bmxerrds: bus error from cpu data access bit (disabled in debug mode) 1 = enable bus error exceptions for unmapped address accesses initiated from cpu data access 0 = disable bus error exceptions for unmapped address accesses initiated from cpu data access bit 16 bmxerris: bus error from cpu instruction access bit (disabled in debug mode) 1 = enable bus error exceptions for unmapped addr ess accesses initiated from cpu instruction access 0 = disable bus error exceptions for unmapped addr ess accesses initiated from cpu instruction access bit 15-7 unimplemented: read as ? 0 ? bit 6 bmxwsdrm: cpu instruction or data access from data ram wait state bit 1 = data ram accesses from cpu have one wait state for address setup 0 = data ram accesses from cpu have zero wait states for address setup bit 5-3 unimplemented: read as ? 0 ? bit 2-0 bmxarb<2:0>: bus matrix arbitration mode bits 111 = reserved (using these configuration modes will produce undefined behavior) ? ? ? 011 = reserved (using these configuration modes will produce undefined behavior) 010 = arbitration mode 2 001 = arbitration mode 1 (default) 000 = arbitration mode 0
pic32mx330/350/370/430/450/470 ds60001185b-page 88 preliminary ? 2012-2013 microchip technology inc. register 4-2: bmxdkpba: data ram ke rnel program base address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 bmxdkpba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdkpba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-10 bmxdkpba<15:10>: drm kernel program base address bits when non-zero, this value selects the relative base address for kernel program space in ram bit 9-0 bmxdkpba<9:0>: read-only bits value is always ? 0 ?, which forces 1 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxdrmsz.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 89 pic32mx330/350/370/430/450/470 register 4-3: bmxdudba: data ram user data base address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 bmxdudba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdudba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-10 bmxdudba<15:10>: drm user data base address bits when non-zero, the value selects the relative base a ddress for user mode data space in ram, the value must be greater than bmxdkpba. bit 9-0 bmxdudba<9:0>: read-only bits value is always ? 0 ?, which forces 1 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxdrmsz.
pic32mx330/350/370/430/450/470 ds60001185b-page 90 preliminary ? 2012-2013 microchip technology inc. register 4-4: bmxdupba: data ram u ser program base address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 bmxdupba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxdupba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-10 bmxdupba<15:10>: drm user program base address bits when non-zero, the value selects the relative base address for user mode program space in ram, bmxdupba must be greater than bmxdudba. bit 9-0 bmxdupba<9:0>: read-only bits value is always ? 0 ?, which forces 1 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxdrmsz.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 91 pic32mx330/350/370/430/450/470 register 4-5: bmxdrmsz: data ram size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrr r r r bmxdrmsz<31:24> 23:16 rrrrr r r r bmxdrmsz<23:16> 15:8 rrrrr r r r bmxdrmsz<15:8> 7:0 rrrrr r r r bmxdrmsz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 bmxdrmsz<31:0>: data ram memory (drm) size bits static value that indicates the size of the data ram in bytes: 0x00004000 = device has 16 kb ram 0x00008000 = device has 32 kb ram 0x00010000 = device has 64 kb ram 0x00020000 = device has 128 kb ram register 4-6: bmxpupba: program fla sh (pfm) user program base address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? bmxpupba<19:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-0 bmxpupba<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 bmxpupba<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-20 unimplemented: read as ? 0 ? bit 19-11 bmxpupba<19:11>: program flash (pfm) user program base address bits bit 10-0 bmxpupba<10:0>: read-only bits value is always ? 0 ?, which forces 2 kb increments note 1: at reset, the value in this register is forced to zero, which causes all of the ram to be allocated to kernal mode data usage. 2: the value in this register must be less than or equal to bmxpfmsz.
pic32mx330/350/370/430/450/470 ds60001185b-page 92 preliminary ? 2012-2013 microchip technology inc. register 4-7: bmxpfmsz: program flash (pfm) size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rrrrr r r r bmxpfmsz<31:24> 23:16 rrrrr r r r bmxpfmsz<23:16> 15:8 rrrrr r r r bmxpfmsz<15:8> 7:0 rrrrr r r r bmxpfmsz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 bmxpfmsz<31:0>: program flash memory (pfm) size bits static value that indicates the size of the pfm in bytes: 0x00010000 = device has 64 kb flash 0x00020000 = device has 128 kb flash 0x00040000 = device has 256 kb flash 0x00080000 = device has 512 kb flash register 4-8: bmxbootsz: boot flash (ifm) size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r r r r r r r r bmxbootsz<31:24> 23:16 r r r r r r r r bmxbootsz<23:16> 15:8 r r r r r r r r bmxbootsz<15:8> 7:0 r r r r r r r r bmxbootsz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 bmxbootsz<31:0>: boot flash memory (bfm) size bits static value that indicates the size of the boot pfm in bytes: 0x00003000 = device has 12 kb boot flash
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 93 pic32mx330/350/370/430/450/470 5.0 flash program memory pic32mx330/350/370/430/45 0/470 devices contain an internal flash program memory for executing user code. there are three methods by which the user can program this memory: ? run-time self-programming (rtsp) ? ejtag programming ? in-circuit serial programming? (icsp?) rtsp is performed by software executing from either flash or ram memory. information about rtsp techniques is available in section 5. ?flash program memory? (ds60001121) in the ?pic32 family reference manual?. ejtag is performed using the ejtag port of the device and an ejtag capable programmer. icsp is performed using a serial data connection to the device and allows much faster programming times than rtsp. the ejtag and icsp methods are described in the ? pic32 flash programming specification ? (ds60001145), which can be downloaded from the microchip web site. note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 5. ?flash program memory? (ds60001121) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. note: on pic32mx330/ 350/370/430/450/470 devices, the flash page size is 4 kb and the row size is 512 bytes (1024 iw and 128 iw, respectively).
pic32mx330/350/370/430/450/470 ds60001185b-page 94 preliminary ? 2012-2013 microchip technology inc. 5.1 control registers register 5-1: nvmcon: programming control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r-0 r-0 r-0 u-0 u-0 u-0 wr wren wrerr (1) lvderr (1) lvdstat (1) ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? nvmop<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 wr: write control bit this bit is writable when wren = 1 and the unlock sequence is followed. 1 = initiate a flash operation. hardware clears this bit when the operation completes 0 = flash operation complete or inactive bit 14 wren: write enable bit 1 = enable writes to wr bit and enables lvd circuit 0 = disable writes to wr bit and disables lvd circuit this is the only bit in this re gister reset by a device reset. bit 13 wrerr: write error bit (1) this bit is read-only and is automatically set by hardware. 1 = program or erase sequence did not complete successfully 0 = program or erase sequence completed normally bit 12 lvderr: low-voltage detect error bit (lvd circuit must be enabled) (1) this bit is read-only and is automatically set by hardware. 1 = low-voltage detected (possible data corruption, if wrerr is set) 0 = voltage level is acceptable for programming bit 11 lvdstat: low-voltage detect status bit (lvd circuit must be enabled) (1) this bit is read-only and is automatic ally set, and cleared, by hardware. 1 = low-voltage event active 0 = low-voltage event not active bit 10-4 unimplemented: read as ? 0 ? bit 3-0 nvmop<3:0>: nvm operation bits these bits are writable when wren = 0 . 1111 = reserved ? ? ? 0111 = reserved 0110 = no operation 0101 = program flash (pfm) erase operation: erases pfm, if all pages are not write-protected 0100 = page erase operation: erases page selected by nvmaddr, if it is not write-protected 0011 = row program operation: programs row select ed by nvmaddr, if it is not write-protected 0010 = no operation 0001 = word program operation: programs word selected by nvmaddr, if it is not write-protected 0000 = no operation note 1: this bit is cleared by setting nvmop == 0000b , and initiating a flash operation (i.e., wr).
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 95 pic32mx330/350/370/430/450/470 register 5-2: nvmkey: programming unlock register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<31:24> 23:16 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<23:16> 15:8 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<15:8> 7:0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 nvmkey<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmkey<31:0>: unlock register bits these bits are write-only, and read as ? 0 ? on any read note 1: this register is used as part of the unlock se quence to prevent inadvertent writes to the pfm. register 5-3: nvmaddr: flash address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmaddr<31:0>: flash address bits bulk/chip/pfm erase: address is ignored. page erase: address identifies the page to erase. row program: address identifies the row to program. word program: address identifies the word to program.
pic32mx330/350/370/430/450/470 ds60001185b-page 96 preliminary ? 2012-2013 microchip technology inc. register 5-4: nvmdata: flash program data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmdata<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmdata<31:0>: flash programming data bits note 1: the bits in this register are only reset by a power-on reset (por). register 5-5: nvmsrcaddr: source data address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 nvmsrcaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 nvmsrcaddr<31:0>: source data address bits the system physical address of th e data to be programmed into the flash when the nvmop<3:0> bits (nvmcon<3:0>) are set to perform row programming.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 97 pic32mx330/350/370/430/450/470 6.0 resets the reset module combines all reset sources and controls the device master reset signal, sysrst. the following is a list of device reset sources: ? por: power-on reset ? mclr : master clear reset pin ? swr: software reset ? wdtr: watchdog timer reset ? bor: brown-out reset ? cmr: configuration mismatch reset ? hvdr: high voltage detect reset a simplified block diagram of the reset module is illustrated in figure 6-1 . figure 6-1: system reset block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 7. ?resets? (ds60001118) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. mclr v dd v dd rise detect por sleep or idle brown-out reset wdt time-out glitch filter bor configuration sysrst software reset power-up timer voltage enabled reset wdtr swr cmr mclr mismatch regulator brown-out reset hvdr v cap hvd detect and reset
pic32mx330/350/370/430/450/470 ds60001185b-page 98 preliminary ? 2012-2013 microchip technology inc. 6.1 control registers register 6-1: rcon: re set control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ? hvdr ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0, hs r/w-0 ? ? ? ? ? ? cmr vregs 7:0 r/w-0, hs r/w-0, hs u-0 r/w-0, hs r/w-0, hs r/w-0, hs r/w-1, hs r/w-1, hs extr swr ? wdto sleep idle bor (1) por (1) legend: hs = set by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-30 unimplemented: read as ? 0 ? bit 29 hvdr: high voltage detect reset flag bit 1 = high voltage detect (hvd) reset has occurred 0 = hvd reset has not occurred bit 28-10 unimplemented: read as ? 0 ? bit 9 cmr: configuration mismatch reset flag bit 1 = configuration mismatch reset has occurred 0 = configuration mismatch reset has not occurred bit 8 vregs: voltage regulator standby enable bit 1 = regulator is enabled and is on during sleep mode 0 = regulator is disabled and is off during sleep mode bit 7 extr: external reset ( mclr ) pin flag bit 1 = master clear (pin) reset has occurred 0 = master clear (pin) reset has not occurred bit 6 swr: software reset flag bit 1 = software reset was executed 0 = software reset as not executed bit 5 unimplemented: read as ? 0 ? bit 4 wdto: watchdog timer time-out flag bit 1 = wdt time-out has occurred 0 = wdt time-out has not occurred bit 3 sleep: wake from sleep flag bit 1 = device was in sleep mode 0 = device was not in sleep mode bit 2 idle: wake from idle flag bit 1 = device was in idle mode 0 = device was not in idle mode bit 1 bor: brown-out reset flag bit (1) 1 = brown-out reset has occurred 0 = brown-out reset has not occurred bit 0 por: power-on reset flag bit (1) 1 = power-on rese t has occurred 0 = power-on reset has not occurred note 1: user software must clear this bit to view next detection.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 99 pic32mx330/350/370/430/450/470 register 6-2: rswrst: software reset register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 w-0, hc ? ? ? ? ? ? ?swrst (1) legend: hc = cleared by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-1 unimplemented: read as ? 0 ? bit 0 swrst: software reset trigger bit (1) 1 = enable software reset event 0 = no effect note 1: the system unlock sequence must be performed be fore the swrst bit can be written. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
pic32mx330/350/370/430/450/470 ds60001185b-page 100 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 101 pic32mx330/350/370/430/450/470 7.0 interrupt controller pic32mx330/350/370/430/450/ 470 devices generate interrupt requests in response to interrupt events from peripheral modules. the interrupt control module exists externally to the cpu logic and prioritizes the interrupt events before presenting them to the cpu. the pic32mx330/350/370/430/450/470 interrupt mod - ule includes the following features: ? up to 76 interrupt sources ? up to 46 interrupt vectors ? single and multi-vector mode operations ? five external interrupts with edge polarity control ? interrupt proximity timer ? seven user-selectable priority levels for each vector ? four user-selectable subpriority levels within each priority ? dedicated shadow set configurable for any priority level (see the fsrssel<2:0> bits (devcfg3<18:16>) in 27.0 ?special features? for more information) ? software can generate any interrupt ? user-configurable interrupt vector table location ? user-configurable interrupt vector spacing figure 7-1: interrupt controller module block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 8. ?interrupt controller? (ds60001108) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. interrupt controller interrupt requests vector number cpu core priority level shadow set number
pic32mx330/350/370/430/450/470 ds60001185b-page 102 preliminary ? 2012-2013 microchip technology inc. table 7-1: interrupt irq, vector and bit location interrupt source (1) irq # vector # interrupt bit location persistent interrupt flag enable priority sub-priority highest natural order priority ct ? core timer interrupt 0 0 ifs0<0> iec0<0> ipc0<4:2> ipc0<1:0> no cs0 ? core software interrupt 0 1 1 ifs0<1> iec0<1> ipc0<12:10> ipc0<9:8> no cs1 ? core software interrupt 1 2 2 ifs0<2> iec0<2> ipc0<20:18> ipc0<17:16> no int0 ? external interrupt 3 3 ifs0<3> iec0<3> ipc0<28:26> ipc0<25:24> no t1 ? timer1 4 4 ifs0<4> iec0<4> ipc1<4:2> ipc1<1:0> no ic1e ? input capture 1 error 5 5 ifs0<5> iec0<5> ipc1<12:10> ipc1<9:8> yes ic1 ? input capture 1 6 5 ifs0<6> iec0<6> ipc1<12:10> ipc1<9:8> yes oc1 ? output compare 1 7 6 ifs0<7> iec0<7> ipc1<20:18> ipc1<17:16> no int1 ? external interrupt 1 8 7 ifs0<8> iec0<8> ipc1<28:26> ipc1<25:24> no t2 ? timer2 9 8 ifs0<9> iec0<9> ipc2<4:2> ipc2<1:0> no ic2e ? input capture 2 10 9 ifs0<10> iec0<10> ipc2<12:10> ipc2<9:8> yes ic2 ? input capture 2 11 9 ifs0<11> iec0<11> ipc2<12:10> ipc2<9:8> yes oc2 ? output compare 2 12 10 ifs0<12> iec0<12> ipc2<20:18> ipc2<17:16> no int2 ? external interrupt 2 13 11 ifs0<13> iec0<13> ipc2<28:26> ipc2<25:24> no t3 ? timer3 14 12 ifs0<14> iec0<14> ipc3<4:2> ipc3<1:0> no ic3e ? input capture 3 15 13 ifs0<15> iec0<15> ipc3<12:10> ipc3<9:8> yes ic3 ? input capture 3 16 13 ifs0<16> iec0<16> ipc3<12:10> ipc3<9:8> yes oc3 ? output compare 3 17 14 ifs0<17> iec0<17> ipc3<20:18> ipc3<17:16> no int3 ? external interrupt 3 18 15 ifs0<18> iec0<18> ipc3<28:26> ipc3<25:24> no t4 ? timer4 19 16 ifs0<19> iec0<19> ipc4<4:2> ipc4<1:0> no ic4e ? input capture 4 error 20 17 ifs0<20> iec0<20> ipc4<12:10> ipc4<9:8> yes ic4 ? input capture 4 21 17 ifs0<21> iec0<21> ipc4<12:10> ipc4<9:8> yes oc4 ? output compare 4 22 18 ifs0<22> iec0<22> ipc4<20:18> ipc4<17:16> no int4 ? external interrupt 4 23 19 ifs0<23> iec0<23> ipc4<28:26> ipc4<25:24> no t5 ? timer5 24 20 ifs0<24> iec0<24> ipc5<4:2> ipc5<1:0> no ic5e ? input capture 5 error 25 21 ifs0<25> iec0<25> ipc5<12:10> ipc5<9:8> yes ic5 ? input capture 5 26 21 ifs0<26> iec0<26> ipc5<12:10> ipc5<9:8> yes oc5 ? output compare 5 27 22 ifs0<27> iec0<27> ipc5<20:18> ipc5<17:16> no ad1 ? adc1 convert done 28 23 ifs0<28> iec0<28> ipc5<28:26> ipc5<25:24> yes fscm ? fail-safe clock monitor 29 24 ifs0<29> iec0<29> ipc6<4:2> ipc6<1:0> no rtcc ? real-time clock and calendar 30 25 ifs0<30> iec0<30> ipc6<12:10> ipc6<9:8> no fce ? flash control event 31 26 ifs0<31> iec0<31> ipc6<20:18> ipc6<17:16> no cmp1 ? comparator interrupt 32 27 ifs1<0> iec1<0> ipc6<28:26> ipc6<25:24> no cmp2 ? comparator interrupt 33 28 ifs1<1> iec1<1> ipc7<4:2> ipc7<1:0> no usb ? usb interrupts 34 29 ifs1<2> iec1<2> ipc7<12:10> ipc7<9:8> yes spi1e ? spi1 fault 35 30 ifs1<3> iec1<3> ipc7<20:18> ipc7<17:16> yes spi1rx ? spi1 receive done 36 30 ifs1<4> iec1<4> ipc7<20:18> ipc7<17:16> yes spi1tx ? spi1 transfer done 37 30 ifs1<5> iec1<5> ipc7<20:18> ipc7<17:16> yes u1e ? uart1 fault 38 31 ifs1<6> iec1<6> ipc7<28:26> ipc7<25:24> yes u1rx ? uart1 receive done 39 31 ifs1<7> iec1<7> ipc7<28:26> ipc7<25:24> yes u1tx ? uart1 transfer done 40 31 ifs1<8> iec1<8> ipc7<28:26> ipc7<25:24> yes i2c1b ? i2c1 bus collision event 41 32 ifs1<9> iec1<9> ipc8<4:2> ipc8<1:0> yes i2c1s ? i2c1 slave event 42 32 ifs1<10> iec1<10> ipc8<4:2> ipc8<1:0> yes i2c1m ? i2c1 master event 43 32 ifs1<11> iec1<11> ipc8<4:2> ipc8<1:0> yes cna ? porta input change interrupt 44 33 ifs1<12> iec1<12> ipc8<12:10> ipc8<9:8> yes note 1: not all interrupt sources are available on all devices. see table 1: ?pic32mx330/350/370/430/450/470 controller family features? for the list of available peripherals.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 103 pic32mx330/350/370/430/450/470 cnb ? portb input change interrupt 45 33 ifs1<13> iec1<13> ipc8<12:10> ipc8<9:8> yes cnc ? portc input change interrupt 46 33 ifs1<14> iec1<14> ipc8<12:10> ipc8<9:8> yes cnd ? portd input change interrupt 47 33 ifs1<15> iec1<15> ipc8<12:10> ipc8<9:8> yes cne ? porte input change interrupt 48 33 ifs1<16> iec1<16> ipc8<12:10> ipc8<9:8> yes cnf ? portf input change interrupt 49 33 ifs1<17> iec1<17> ipc8<12:10> ipc8<9:8> yes cng ? portg input change interrupt 50 33 ifs1<18> iec1<18> ipc8<12:10> ipc8<9:8> yes pmp ? parallel master port 51 34 ifs1<19> iec1<19> ipc8<20:18> ipc8<17:16> yes pmpe ? parallel master port error 52 34 ifs1<20> iec1<20> ipc8<20:18> ipc8<17:16> yes spi2e ? spi2 fault 53 35 ifs1<21> iec1<21> ipc8<28:26> ipc8<25:24> yes spi2rx ? spi2 receive done 54 35 ifs1<22> iec1<22> ipc8<28:26> ipc8<25:24> yes spi2tx ? spi2 transfer done 55 35 ifs1<23> iec1<23> ipc8<28:26> ipc8<25:24> yes u2e ? uart2 error 56 36 ifs1<24> iec1<24> ipc9<4:2> ipc9<1:0> yes u2rx ? uart2 receiver 57 36 ifs1<25> iec1<25> ipc9<4:2> ipc9<1:0> yes u2tx ? uart2 transmitter 58 36 ifs1<26> iec1<26> ipc9<4:2> ipc9<1:0> yes i2c2b ? i2c2 bus collision event 59 37 ifs1<27> iec1<27> ipc9<12:10> ipc9<9:8> yes i2c2s ? i2c2 slave event 60 37 ifs1<28> iec1<28> ipc9<12:10> ipc9<9:8> yes i2c2m ? i2c2 master event 61 37 ifs1<29> iec1<29> ipc9<12:10> ipc9<9:8> yes u3e ? uart3 error 62 38 ifs1<30> iec1<30> ipc9<20:18> ipc9<17:16> yes u3rx ? uart3 receiver 63 38 ifs1<31> iec1<31> ipc9<20:18> ipc9<17:16> yes u3tx ? uart3 transmitter 64 38 ifs2<0> iec2<0> ipc9<20:18> ipc9<17:16> yes u4e ? uart4 error 65 39 ifs2<1> iec2<1> ipc9<28:26> ipc9<25:24> yes u4rx ? uart4 receiver 66 39 ifs2<2> iec2<2> ipc9<28:26> ipc9<25:24> yes u4tx ? uart4 transmitter 67 39 ifs2<3> iec2<3> ipc9<28:26> ipc9<25:24> yes u5e ? uart5 error 68 40 ifs2<4> iec2<4> ipc10<4:2> ipc10<1:0> yes u5rx ? uart5 receiver 69 40 ifs2<5> iec2<5> ipc10<4:2> ipc10<1:0> yes u5tx ? uart5 transmitter 70 40 ifs2<6> iec2<6> ipc10<4:2> ipc10<1:0> yes ctmu ? ctmu event 71 41 ifs2<7> iec2<7> ipc10<12:10> ipc10<9:8> yes dma0 ? dma channel 0 72 42 ifs2<8> iec2<8> ipc10<20:18> ipc10<17:16> yes dma1 ? dma channel 1 73 43 ifs2<9> iec2<9> ipc10<28:26> ipc10<25:24> yes dma2 ? dma channel 2 74 44 ifs2<10> iec2<10> ipc11<4:2> ipc11<1:0> yes dma3 ? dma channel 3 75 45 ifs2<11> iec2<11> ipc11<12:10> ipc11<9:8> yes lowest natural order priority table 7-1: interrupt irq, vector and bit location (continued) interrupt source (1) irq # vector # interrupt bit location persistent interrupt flag enable priority sub-priority note 1: not all interrupt sources are available on all devices. see table 1: ?pic32mx330/350/370/430/450/470 controller family features? for the list of available peripherals.
pic32mx330/350/370/430/450/470 ds60001185b-page 104 preliminary ? 2012-2013 microchip technology inc. 7.1 interrupts control registers register 7-1: intcon: interrupt control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? ss0 15:8 u-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? mvec ? tpc<2:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? int4ep int3ep int2ep int1ep int0ep legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-17 unimplemented: read as ? 0 ? bit 16 ss0: single vector shadow register set bit 1 = single vector is presented with a shadow register set 0 = single vector is not present ed with a shadow register set bit 15-13 unimplemented: read as ? 0 ? bit 12 mvec: multi vector configuration bit 1 = interrupt controller confi gured for multi vectored mode 0 = interrupt controller configured for single vectored mode bit 11 unimplemented: read as ? 0 ? bit 10-8 tpc<2:0>: interrupt proximity timer control bits 111 = interrupts of group priority 7 or lo wer start the interrupt proximity timer 110 = interrupts of group priority 6 or lo wer start the interrupt proximity timer 101 = interrupts of group priority 5 or lo wer start the interrupt proximity timer 100 = interrupts of group priority 4 or lo wer start the interrupt proximity timer 011 = interrupts of group priority 3 or lo wer start the interrupt proximity timer 010 = interrupts of group priority 2 or lo wer start the interrupt proximity timer 001 = interrupts of group priority 1 start the interrupt proximity timer 000 = disables interrupt proximity timer bit 7-5 unimplemented: read as ? 0 ? bit 4 int4ep: external interrupt 4 edge polarity control bit 1 = rising edge 0 = falling edge bit 3 int3ep: external interrupt 3 edge polarity control bit 1 = rising edge 0 = falling edge bit 2 int2ep: external interrupt 2 edge polarity control bit 1 = rising edge 0 = falling edge bit 1 int1ep: external interrupt 1 edge polarity control bit 1 = rising edge 0 = falling edge bit 0 int0ep: external interrupt 0 edge polarity control bit 1 = rising edge 0 = falling edge
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 105 pic32mx330/350/370/430/450/470 register 7-2: intstat: interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ?sripl<2:0> (1) 7:0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vec<5:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-11 unimplemented: read as ? 0 ? bit 10-8 sripl<2:0>: requested priority level bits (1) 000-111 = the priority level of the late st interrupt presented to the cpu bit 7-6 unimplemented: read as ? 0 ? bit 5-0 vec<5:0>: interrupt vector bits (1) 00000-11111 = the interrupt vector that is presented to the cpu note 1: this value should only be used when the interr upt controller is configured for single vector mode. register 7-3: iptmr: interrupt proximity timer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iptmr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 iptmr<31:0>: interrupt proximity timer reload bits used by the interrupt proximity timer as a reload va lue when the interrupt proximity timer is triggered by an interrupt event.
pic32mx330/350/370/430/450/470 ds60001185b-page 106 preliminary ? 2012-2013 microchip technology inc. register 7-4: ifsx: interru pt flag status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs31 ifs30 ifs29 ifs28 ifs27 ifs26 ifs25 ifs24 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs23 ifs22 ifs21 ifs20 ifs19 ifs18 ifs17 ifs16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs15 ifs14 ifs13 ifs12 ifs11 ifs10 ifs9 ifs8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ifs7 ifs6 ifs5 ifs4 ifs3 ifs2 ifs1 ifs0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 ifs31-ifs0: interrupt flag status bits 1 = interrupt request has occurred 0 = no interrupt request has occurred note 1: this register represents a generic defini tion of the ifsx register. refer to table 7-1 for the exact bit definitions. register 7-5: iecx: interrupt enable control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec31 iec30 iec29 iec28 iec27 iec26 iec25 iec24 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec23 iec22 iec21 iec20 iec19 iec18 iec17 iec16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec15 iec14 iec13 iec12 iec11 iec10 iec9 iec8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 iec7 iec6 iec5 iec4 iec3 iec2 iec1 iec0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 iec31-iec0: interrupt enable bits 1 = interrupt is enabled 0 = interrupt is disabled note 1: this register represents a generic definition of the iecx register. refer to ta b l e 7-1 for the exact bit definitions.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 107 pic32mx330/350/370/430/450/470 register 7-6: ipcx: interrupt priority control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip3<2:0> is3<1:0> 23:16 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip2<2:0> is2<1:0> 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip1<2:0> is1<1:0> 7:0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ip0<2:0> is0<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as ? 0 ? bit 28-26 ip3<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 25-24 is3<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpiority is 0 bit 23-21 unimplemented: read as ? 0 ? bit 20-18 ip2<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 17-16 is2<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 15-13 unimplemented: read as ? 0 ? bit 12-10 ip1<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled note 1: this register represents a generic defini tion of the ipcx register. refer to table 7-1 for the exact bit definitions.
pic32mx330/350/370/430/450/470 ds60001185b-page 108 preliminary ? 2012-2013 microchip technology inc. bit 9-8 is1<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-2 ip0<2:0>: interrupt priority bits 111 = interrupt priority is 7 ? ? ? 010 = interrupt priority is 2 001 = interrupt priority is 1 000 = interrupt is disabled bit 1-0 is0<1:0>: interrupt subpriority bits 11 = interrupt subpriority is 3 10 = interrupt subpriority is 2 01 = interrupt subpriority is 1 00 = interrupt subpriority is 0 register 7-6: ipcx: interrupt priority control register (continued) note 1: this register represents a generic definition of the ipcx register. refer to table 7-1 for the exact bit definitions.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 109 pic32mx330/350/370/430/450/470 8.0 oscillator configuration the pic32mx330/350/370/430/450/470 oscillator system has the following modules and features: ? a total of four external and internal oscillator options as clock sources ? on-chip pll with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources ? on-chip user-selectable divisor postscaler on select oscillator sources ? software-controllable switching between ? various clock sources ? a fail-safe clock monitor (fscm) that detects clock failure and permits safe application recovery or shutdown ? dedicated on-chip pll for usb peripheral a block diagram of the oscilla tor system is provided in figure 8-1 . note 1: this data sheet summarizes the features of the pic32mx330/350/370/ 430/450/470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 6. ?oscillator configuration? (ds60001112) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information.
pic32mx330/350/370/430/450/470 ds60001185b-page 110 preliminary ? 2012-2013 microchip technology inc. figure 8-1: pic32mx330/350/370/43 0/450/470 family clock diagram notes: 1. a series resistor, r s , may be required for at strip cut crystals or eliminate c lipping. alternately, to increase oscillator circuit gain, add a parallel resistor, r p , with a value of 1 m ?? 2. the internal feedback resistor, r f , is typically in the range of 2 to 10 m ?? 3. refer to section 6. ?oscillator configuration? (ds60001112) in the ? pic32 family reference manual ? for help in determining the best oscillator components. 4. pbclk out is available on the osc2 pin in certain clock modes. 5. usb pll is available on pic32mx4xx devices only. timer1, rtcc clock control logic fail-safe clock monitor fscm int fscm event cosc<2:0> nosc<2:0> oswen fscmen<1:0> pll secondary oscillator (s osc ) soscen and fsoscen sosco sosci primary oscillator p osc (xt, hs, ec) cpu and select peripherals peripherals frcdiv<2:0> wdt, pwrt 8 mhz typical frc 31.25 khz typical frc oscillator lprc oscillator s osc lprc frcdiv tun<5:0> div 16 postscaler fpllidiv<2:0> pbdiv<1:0> frc/16 postscaler cosc<2:0> f in div x div y pllodiv<2:0> div x 32.768 khz pllmult<2:0> pbclk (t pb ) uf in ?? 4 mhz pll x24 usb clock (48 mhz) div 2 upllen ufrcen div x upllidiv<2:0> uf in 4 mhz ?? f in ?? 5 mhz c1 (3) c2 (3) xtal r s (1) enable osc2 (4) osc1 r f (2) to internal logic usb pll (5) (p osc ) div 2 to a d c sysclk refclki refclko oe to s p i rosel<3:0> p osc frc lprc s osc pbclk sysclk xtpll, hspll, ecpll, frcpll system usb pll 2n m 512 --------- - + ?? ?? ? rodiv<4:0> (n) rotrim<8:0> (m) r p (1) ?
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 111 pic32mx330/350/370/430/450/470 8.1 control registers register 8-1: osccon: osci llator control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 r/w-y r/w-y r/w-y r/w-0 r/w-0 r/w-1 ? ? pllodiv<2:0> frcdiv<2:0> 23:16 u-0 r-0 r-1 r/w-y r/w-y r/w-y r/w-y r/w-y ? soscrdy pbdivrdy pbdiv<1:0> pllmult<2:0> 15:8 u-0 r-0 r-0 r-0 u-0 r/w-y r/w-y r/w-y ? cosc<2:0> ? nosc<2:0> 7:0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-y r/w-0 clklock ulock (1) slock slpen cf ufrcen (1) soscen oswen legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-30 unimplemented: read as ? 0 ? bit 29-27 pllodiv<2:0>: output divider for pll 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 bit 26-24 frcdiv<2:0>: internal fast rc (frc) oscillator clock divider bits 111 = frc divided by 256 110 = frc divided by 64 101 = frc divided by 32 100 = frc divided by 16 011 = frc divided by 8 010 = frc divided by 4 001 = frc divided by 2 (default setting) 000 = frc divided by 1 bit 23 unimplemented: read as ? 0 ? bit 22 soscrdy: secondary oscillator (s osc ) ready indicator bit 1 = indicates that the secondary oscillator is running and is stable 0 = secondary oscillator is still warming up or is turned off bit 21 pbdivrdy: peripheral bus clock (pbclk) divisor ready bit 1 = pbdiv<1:0> bits can be written 0 = pbdiv<1:0> bits cannot be written bit 20-19 pbdiv<1:0>: peripheral bus clock (pbclk) divisor bits 11 = pbclk is sysclk divided by 8 (default) 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 note 1: this bit is available on pic32mx4xx devices only. note: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
pic32mx330/350/370/430/450/470 ds60001185b-page 112 preliminary ? 2012-2013 microchip technology inc. bit 18-16 pllmult<2:0>: phase-locked loop (pll) multiplier bits 111 = clock is multiplied by 24 110 = clock is multiplied by 21 101 = clock is multiplied by 20 100 = clock is multiplied by 19 011 = clock is multiplied by 18 010 = clock is multiplied by 17 001 = clock is multiplied by 16 000 = clock is multiplied by 15 bit 15 unimplemented: read as ? 0 ? bit 14-12 cosc<2:0>: current oscillator selection bits 111 = internal fast rc (frc) oscillat or divided by osccon bits 110 = internal fast rc (frc) oscillator divided by 16 101 = internal low-power rc (lprc) oscillator 100 = secondary oscillator (s osc ) 011 = primary oscillator (p osc ) with pll module (xtpll, hspll or ecpll) 010 = primary oscillator (p osc ) (xt, hs or ec) 001 = internal fast rc oscillator with pll module via postscaler (frcpll) 000 = internal fast rc (frc) oscillator bit 11 unimplemented: read as ? 0 ? bit 10-8 nosc<2:0>: new oscillator selection bits 111 = internal fast rc oscillator (f rc) divided by osccon bits 110 = internal fast rc osc illator (frc) divided by 16 101 = internal low-power rc (lprc) oscillator 100 = secondary oscillator (s osc ) 011 = primary oscillator with pll module (xtpll, hspll or ecpll) 010 = primary oscillator (xt, hs or ec) 001 = internal fast internal rc oscillator with pll module via postscaler (frcpll) 000 = internal fast internal rc oscillator (frc) on reset, these bits are set to the value of the fnosc configuration bits (devcfg1<2:0>). bit 7 clklock: clock selection lock enable bit if clock switching and monitoring is disabled ( fcksm<1:0> = 1x ): 1 = clock and pll selections are locked 0 = clock and pll selections are not locked and may be modified if clock switching and monitoring is enabled (fcksm<1:0> = 0x ): clock and pll selections are never locked and may be modified. bit 6 ulock: usb pll lock status bit (1) 1 = indicates that the usb pll module is in lock or usb pll module start-up timer is satisfied 0 = indicates that the usb pll module is out of lock or usb pll module start-up timer is in progress or usb pll is disabled bit 5 slock: pll lock status bit 1 = pll module is in lock or pll module start-up timer is satisfied 0 = pll module is out of lock, pll start-up timer is running or pll is disabled bit 4 slpen: sleep mode enable bit 1 = device will enter sleep mode when a wait instruction is executed 0 = device will enter idle mode when a wait instruction is executed register 8-1: osccon: oscillator control register (continued) note 1: this bit is available on pic32mx4xx devices only. note: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 113 pic32mx330/350/370/430/450/470 bit 3 cf: clock fail detect bit 1 = fscm has detected a clock failure 0 = no clock failure has been detected bit 2 ufrcen: usb frc clock enable bit (1) 1 = enable frc as the clock so urce for the usb clock source 0 = use the primary oscillator or usb pll as the usb clock source bit 1 soscen: secondary oscillator (s osc ) enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 0 oswen: oscillator switch enable bit 1 = initiate an oscillator switch to selection specified by nosc<2:0> bits 0 = oscillator switch is complete register 8-1: osccon: oscillator control register (continued) note 1: this bit is available on pic32mx4xx devices only. note: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
pic32mx330/350/370/430/450/470 ds60001185b-page 114 preliminary ? 2012-2013 microchip technology inc. register 8-2: osctun: frc tuning register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? tun<5:0> (1) legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-6 unimplemented: read as ? 0 ? bit 5-0 tun<5:0>: frc oscillator tuning bits (1) 100000 = center frequency -12.5% 100001 = ? ? ? 111111 = 000000 = center frequency. oscillator runs at minimal frequency (8 mhz) 000001 = ? ? ? 011110 = 011111 = center frequency +12.5% note 1: osctun functionality has been provided to help cust omers compensate for temperature effects on the frc frequency over a wide range of temperatures. the tu ning step size is an approximation, and is neither characterized, nor tested. note: writes to this register require an unlock sequence. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 115 pic32mx330/350/370/430/450/470 register 8-3: refocon: referenc e oscillator control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? rodiv<14:8> (3) 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rodiv<7:0> (3) 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0, hc r-0, hs, hc on ?sidloe rslp (2) ? divswen active 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? rosel<3:0> (1) legend: hc = hardware clearable hs = hardware settable r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 unimplemented: read as ? 0 ? bit 30-16 rodiv<14:0>: reference clock divider bits (1) this value selects the reference clock divider bits. see figure 8-1 for more information. bit 15 on: output enable bit 1 = reference oscillator module enabled 0 = reference oscillator module disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: peripheral stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 oe: reference clock output enable bit 1 = reference clock is driven out on refclko pin 0 = reference clock is not driven out on refclko pin bit 11 rslp: reference oscillator module run in sleep bit (2) 1 = reference oscillator module output continues to run in sleep 0 = reference oscillator module output is disabled in sleep bit 10 unimplemented: read as ? 0 ? bit 9 divswen: divider switch enable bit 1 = divider switch is in progress 0 = divider switch is complete bit 8 active: reference clock request status bit 1 = reference clock request is active 0 = reference clock request is not active bit 7-4 unimplemented: read as ? 0 ? note 1: the rosel and rodiv bits should not be written while the active bit is ? 1 ?, as undefined behavior may result. 2: this bit is ignored when the rosel<3:0> bits = 0000 or 0001 . 3: while the on bit is set to ? 1 ?, writes to these bits do not take effe ct until the divswen bit is also set to ? 1 ?.
pic32mx330/350/370/430/450/470 ds60001185b-page 116 preliminary ? 2012-2013 microchip technology inc. bit 3-0 rosel<3:0>: reference clock source select bits (1) 1111 = reserved; do not use ? ? ? 1001 = reserved; do not use 1000 = refclki 0111 = system pll output 0110 = usb pll output 0101 =s osc 0100 =lprc 0011 =frc 0010 =p osc 0001 = pbclk 0000 = sysclk register 8-3: refocon: reference oscillator control register (continued) note 1: the rosel and rodiv bits should not be written while the active bit is ? 1 ?, as undefined behavior may result. 2: this bit is ignored when the rosel<3:0> bits = 0000 or 0001 . 3: while the on bit is set to ? 1 ?, writes to these bits do not take effe ct until the divswen bit is also set to ? 1 ?.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 117 pic32mx330/350/370/430/450/470 register 8-4: refotrim: refere nce oscillator trim register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rotrim<8:1> 23:16 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 rotrim<0> ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: y = value set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-23 rotrim<8:0>: reference oscillator trim bits 111111111 = 511/512 divisor added to rodiv value 111111110 = 510/512 divisor added to rodiv value ? ? ? 100000000 = 256/512 divisor added to rodiv value ? ? ? 000000010 = 2/512 divisor added to rodiv value 000000001 = 1/512 divisor added to rodiv value 000000000 = 0/512 divisor added to rodiv value bit 22-0 unimplemented: read as ? 0 ? note 1: while the on bit (refocon<15>) is ? 1 ?, writes to this register do not ta ke effect until the divswen bit is also set to ? 1 ?.
pic32mx330/350/370/430/450/470 ds60001185b-page 118 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 119 pic32mx330/350/370/430/450/470 9.0 prefetch cache prefetch cache increases performance for applications executing out of the cacheable program flash memory regions by implementing inst ruction caching, constant data caching and instruction prefetching. 9.1 features ? 16 fully associative lockable cache lines ? 16-byte cache lines ? up to four cache lines allocated to data ? two cache lines with address mask to hold repeated instructions ? pseudo lru replacement policy ? all cache lines are software writable ? 16-byte parallel memory fetch ? predictive instruction prefetch a simplified block diagram of the prefetch cache module is illustrated in figure 9-1 . figure 9-1: prefetch cache module block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 4. ?prefetch cache? (ds60001119) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. ctrl rdata prefetch prefetch hit logic cache line address encode cache line fsm ctrl rdata tag logic bus control cache control prefetch control hit lru miss lru bmx/cpu bmx/cpu ctrl pfm
pic32mx330/350/370/430/450/470 ds60001185b-page 120 preliminary ? 2012-2013 microchip technology inc. 9.2 control registers register 9-1: checon: cache control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? checoh 15:8 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? dcsz<1:0> 7:0 u-0 u-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ? ? prefen<1:0> ?pfmws<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-17 unimplemented: write ? 0 ?; ignore read bit 16 checoh: cache coherency setting on a pfm program cycle bit 1 = invalidate all data and instruction lines 0 = invalidate all data lnes and in struction lines that are not locked bit 15-10 unimplemented: write ? 0 ?; ignore read bit 9-8 dcsz<1:0>: data cache size in lines bits 11 = enable data caching with a size of 4 lines 10 = enable data caching with a size of 2 lines 01 = enable data caching with a size of 1 line 00 = disable data caching changing these bits induce all lines to be reinitialized to the ?invalid? state. bit 7-6 unimplemented: write ? 0 ?; ignore read bit 5-4 prefen<1:0>: predictive prefetch enable bits 11 = enable predictive prefetch for both cacheable and non-cacheable regions 10 = enable predictive prefetch for non-cacheable regions only 01 = enable predictive prefetch for cacheable regions only 00 = disable predictive prefetch bit 3 unimplemented: write ? 0 ?; ignore read bit 2-0 pfmws<2:0>: pfm access time defined in te rms of syslk wait states bits 111 = seven wait states 110 = six wait states 101 = five wait states 100 = four wait states 011 = three wait states 010 = two wait states 001 = one wait state 000 = zero wait state
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 121 pic32mx330/350/370/430/450/470 register 9-2: cheacc: cache access register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 chewen ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? cheidx<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 chewen: cache access enable bits for registers chetag, chemsk, chew0, chew1, chew2, and chew3 1 = the cache line selected by cheidx<3:0> is writeable 0 = the cache line selected by cheidx<3:0> is not writeable bit 30-4 unimplemented: write ? 0 ?; ignore read bit 3-0 cheidx<3:0>: cache line index bits the value selects the cache line for reading or writing.
pic32mx330/350/370/430/450/470 ds60001185b-page 122 preliminary ? 2012-2013 microchip technology inc. register 9-3: chetag: cache tag register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ltagboot ? ? ? ? ? ? ? 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ltag<19:12> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ltag<11:4> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-0 r/w-0 r/w-1 u-0 ltag<3:0> lvalid llock ltype ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 ltagboot: line tag address boot bit 1 = the line is in the 0x1d000000 (physical) area of memory 0 = the line is in the 0x1fc00000 (physical) area of memory bit 30-24 unimplemented: write ? 0 ?; ignore read bit 23-4 ltag<19:0>: line tag address bits ltag<19:0> bits are compared against physical address to determine a hit. because its address range and position of pfm in kernel space and user space, the ltag pfm address is identical for virtual addresses, (system) physical addresses, and pfm physical addresses. bit 3 lvalid: line valid bit 1 = the line is valid and is compared to the physical address for hit detection 0 = the line is not valid and is not compared to the physical address for hit detection bit 2 llock: line lock bit 1 = the line is locked and will not be replaced 0 = the line is not locked and can be replaced bit 1 ltype: line type bit 1 = the line caches instruction words 0 = the line caches data words bit 0 unimplemented: write ? 0 ?; ignore read
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 123 pic32mx330/350/370/430/450/470 register 9-4: chemsk: c ache tag mask register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lmask<10:3> 7:0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 lmask<2:0> ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: write ? 0 ?; ignore read bit 15-5 lmask<10:0>: line mask bits 1 = enables mask logic to force a match on the corresponding bit position in ltag<19:0> bits (chetag<23:4>) and the physical address. 0 = only writeable for values of cheidx<3:0> bits (cheacc<3:0>) equal to 0x0a and 0x0b. ? disables mask logic. bit 4-0 unimplemented: write ? 0 ?; ignore read register 9-5: chew0: cache word 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew0<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chew0<31:0>: word 0 of the cache line selected by cheidx<3:0> bits (cheacc<3:0>) readable only if the device is not code-protected.
pic32mx330/350/370/430/450/470 ds60001185b-page 124 preliminary ? 2012-2013 microchip technology inc. register 9-6: chew1: cache word 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew1<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chew1<31:0>: word 1 of the cache line selected by cheidx<3:0> bits (cheacc<3:0>) readable only if the device is not code-protected. register 9-7: chew2: cache word 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew2<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chew2<31:0>: word 2 of the cache line selected by cheidx<3:0> bits (cheacc<3:0>) readable only if the device is not code-protected.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 125 pic32mx330/350/370/430/450/470 register 9-8: chew3: cache word 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chew3<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chew3<31:0>: word 3 of the cache line selected by cheidx<3:0> bits (cheacc<3:0>) readable only if the device is not code-protected. note: this register is a window into the cache data array and is readable only if the dev ice is not code-protected. register 9-9: chelru: cache lru register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 ? ? ? ? ? ? ? chelru<24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chelru<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chelru<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chelru<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-25 unimplemented: write ? 0 ?; ignore read bit 24-0 chelru<24:0>: cache least recently used state encoding bits indicates the pseudo-lru state of the cache.
pic32mx330/350/370/430/450/470 ds60001185b-page 126 preliminary ? 2012-2013 microchip technology inc. register 9-10: chehit: cache hit statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chehit<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chehit<31:0>: cache hit count bits incremented each time the processor issues an instructio n fetch or load that hits the prefetch cache from a cacheable region. non-cacheable accesses do not modify this value. register 9-11: chemis: cach e miss statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chemis<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chemis<31:0>: cache miss count bits incremented each time the processor is sues an instruction fetch from a cacheable region that misses the prefetch cache. non-cacheable acce sses do not modify this value.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 127 pic32mx330/350/370/430/450/470 register 9-12: chepfabt: prefetch cache abort statistics register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<31:24> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<23:16> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<15:8> 7:0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x chepfabt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chepfabt<31:0>: prefab abort count bits incremented each time an automatic pref etch cache is aborted due to a non- sequential instruction fetch, load or store.
pic32mx330/350/370/430/450/470 ds60001185b-page 128 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 129 pic32mx330/350/370/430/450/470 10.0 direct memory access (dma) controller the pic32 direct memory acce ss (dma) controller is a bus master module useful for data transfers between different devices without cpu intervention. the source and destination of a dma transfer can be any of the memory mapped modules exis tent in the pic32 (such as peripheral bus (pbus) devices: spi, uart, pmp, etc.) or memory itself. following are some of the key features of the dma controller module: ? four identical channels, each featuring: - auto-increment source and destination address registers - source and destination pointers - memory to memory and memory to peripheral transfers ? automatic word-size detection: - transfer granularity, down to byte level - bytes need not be word-aligned at source and destination ? fixed priority channel arbitration ? flexible dma channel operating modes: - manual (software) or automatic (interrupt) dma requests - one-shot or auto-repe at block transfer modes - channel-to-channel chaining ? flexible dma requests: - a dma request can be selected from any of the peripheral interrupt sources - each channel can select any (appropriate) observable interrupt as its dma request source - a dma transfer abort can be selected from any of the peripheral interrupt sources - pattern (data) match transfer termination ? multiple dma channel status interrupts: - dma channel block transfer complete - source empty or half empty - destination full or half full - dma transfer aborted due to an external event - invalid dma address generated ? dma debug support features: - most recent address accessed by a dma channel - most recent dma channel to transfer data ? crc generation module: - crc module can be assigned to any of the available channels - crc module is highly configurable figure 10-1: dma block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 31. ?direct memory access (dma) controller? (ds60001117) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. address decoder channel 0 control channel 1 control channel n control global control (dmacon) bus interface channel priority arbitration s e l s e l y i 0 i 1 i 2 i n system irq int controller device bus + bus arbitration peripheral bus
pic32mx330/350/370/430/450/470 ds60001185b-page 130 preliminary ? 2012-2013 microchip technology inc. 10.1 control registers register 10-1: dmacon: dma co ntroller control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 r/w-0 r/w-0 u-0 u-0 u-0 on (1) ? ? suspend dmabusy ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: dma on bit (1) 1 = dma module is enabled 0 = dma module is disabled bit 14-13 unimplemented: read as ? 0 ? bit 12 suspend: dma suspend bit 1 = dma transfers are suspended to allow cpu uninterrupted access to data bus 0 = dma operates normally bit 11 dmabusy: dma module busy bit (4) 1 = dma module is active 0 = dma module is disabled and not actively transferring data bit 10-0 unimplemented: read as ? 0 ? note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 131 pic32mx330/350/370/430/450/470 register 10-2: dmastat: dma status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ? rdwr dmach<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as ? 0 ? bit 3 rdwr: read/write status bit 1 = last dma bus access was a read 0 = last dma bus access was a write bit 2-0 dmach<2:0>: dma channel bits these bits contain the value of the most recent active dma channel. register 10-3: dmaaddr: dma address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<31:24> 23:16 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<23:16> 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 dmaaddr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 dmaaddr<31:0>: dma module address bits these bits contain the address of the most recent dma access.
pic32mx330/350/370/430/450/470 ds60001185b-page 132 preliminary ? 2012-2013 microchip technology inc. register 10-4: dcrccon: dm a crc control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 ? ?byto<1:0>wbo (1) ? ?bito 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? plen<4:0> 7:0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 crcen crcapp (1) crctyp ? ? crcch<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-30 unimplemented: read as ? 0 ? bit 29-28 byto<1:0>: crc byte order selection bits 11 = endian byte swap on half-word boundaries (i.e., sour ce half-word order with reverse source byte order per half-word) 10 = swap half-words on word boundaries (i.e., revers e source half-word order with source byte order per half-word) 01 = endian byte swap on word boundaries (i.e., reverse source byte order) 00 = no swapping (i.e., source byte order) bit 27 wbo: crc write byte order selection bit (1) 1 = source data is written to the destina tion re-ordered as defined by byto<1:0> 0 = source data is written to the destination unaltered bit 26-25 unimplemented: read as ? 0 ? bit 24 bito: crc bit order selection bit (4) when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): 1 = the ip header checksum is calculated least significant bit (lsb) first (i.e., reflected) 0 = the ip header checksum is calculated most significant bit (msb) first (i.e., not reflected) when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): 1 = the lfsr crc is calculated least significant bit first (i.e., reflected) 0 = the lfsr crc is calculated most sign ificant bit first (i.e., not reflected) bit 23-13 unimplemented: read as ? 0 ? bit 12-8 plen<4:0>: polynomial length bits (1) when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): these bits are unused. when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): denotes the length of the polynomial ? 1. bit 7 crcen: crc enable bit 1 = crc module is enabled and channel transfers are routed through the crc module 0 = crc module is disabled and channel transfers proceed normally note 1: when wbo = 1 , unaligned transfers are not support ed and the crcapp bit cannot be set.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 133 pic32mx330/350/370/430/450/470 bit 6 crcapp: crc append mode bit (1) 1 = the dma transfers data from the source into the crc but not to the destination. when a block transfer completes the dma writes the calculated crc value to the location given by chxdsa 0 = the dma transfers data from the source through the crc obeying wbo as it writes the data to the destination bit 5 crctyp: crc type selection bit 1 = the crc module will calculate an ip header checksum 0 = the crc module will calculate a lfsr crc bit 4-3 unimplemented: read as ? 0 ? bit 2-0 crcch<2:0>: crc channel select bits 111 = crc is assigned to channel 7 110 = crc is assigned to channel 6 101 = crc is assigned to channel 5 100 = crc is assigned to channel 4 011 = crc is assigned to channel 3 010 = crc is assigned to channel 2 001 = crc is assigned to channel 1 000 = crc is assigned to channel 0 register 10-4: dcrccon: dma crc control register (continued) note 1: when wbo = 1 , unaligned transfers are not support ed and the crcapp bit cannot be set.
pic32mx330/350/370/430/450/470 ds60001185b-page 134 preliminary ? 2012-2013 microchip technology inc. register 10-5: dcrcdata: dma crc data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcdata<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 dcrcdata<31:0>: crc data register bits writing to this register will seed t he crc generator. reading from this regist er will return the current value of the crc. bits greater than plen will return ? 0 ? on any read. when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): only the lower 16 bits contain ip header checksum information. the upper 16 bits are always ? 0 ?. data written to this register is conver ted and read back in 1?s complement form (i.e., current ip header checksum value). when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): bits greater than plen will return ? 0 ? on any read. register 10-6: dcrcxor: dma crcxor enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dcrcxor<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 dcrcxor<31:0>: crc xor register bits when crctyp (dcrccon<15>) = 1 (crc module is in ip header mode): this register is unused. when crctyp (dcrccon<15>) = 0 (crc module is in lfsr mode): 1 = enable the xor input to the shift register 0 = disable the xor input to the shift register; data is shifted in directly from the previous stage in the register
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 135 pic32mx330/350/370/430/450/470 register 10-7: dchxcon: dma channel ?x? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 chbusy ? ? ? ? ? ? chchns (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r-0 r/w-0 r/w-0 chen (2) chaed chchn chaen ? chedet chpri<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 chbusy: channel busy bit 1 = channel is active or has been enabled 0 = channel is inactive or has been disabled bit 14-9 unimplemented: read as ? 0 ? bit 8 chchns: chain channel selection bit (1) 1 = chain to channel lower in natural priority (ch1 will be enabled by ch2 transfer complete) 0 = chain to channel higher in natural priority (ch1 will be enabled by ch0 transfer complete) bit 7 chen: channel enable bit (2) 1 = channel is enabled 0 = channel is disabled bit 6 chaed: channel allow events if disabled bit 1 = channel start/abort events will be regi stered, even if the channel is disabled 0 = channel start/abort events will be ignored if the channel is disabled bit chchn: channel chain enable bit 1 = allow channel to be chained 0 = do not allow channel to be chained bit 4 chaen: channel automatic enable bit 1 = channel is continuously enabled, and not automat ically disabled after a block transfer is complete 0 = channel is disabled on block transfer complete bit 3 unimplemented: read as ? 0 ? bit 2 chedet: channel event detected bit 1 = an event has been detected 0 = no events have been detected bit 1-0 chpri<1:0>: channel priority bits 11 = channel has priority 3 (highest) 10 = channel has priority 2 01 = channel has priority 1 00 = channel has priority 0 note 1: the chain selection bit takes effect when chaining is enabled (i.e., chchn = 1 ). 2: when the channel is suspended by clearing this bit, the user application should poll the chbusy bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transacti on before the channel is suspended.
pic32mx330/350/370/430/450/470 ds60001185b-page 136 preliminary ? 2012-2013 microchip technology inc. register 10-8: dchxecon: dma cha nnel ?x? event control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chairq<7:0> (1) 15:8 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 chsirq<7:0> (1) 7:0 s-0 s-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 cforce cabort paten sirqen airqen ? ? ? legend: s = settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23-16 chairq<7:0>: channel transfer abort irq bits (1) 11111111 = interrupt 255 will abort any transfers in progress and set chaif flag ? ? ? 00000001 = interrupt 1 will abort any transfers in progress and set chaif flag 00000000 = interrupt 0 will abort any transfers in progress and set chaif flag bit 15-8 chsirq<7:0>: channel transfer start irq bits (1) 11111111 = interrupt 255 will initiate a dma transfer ? ? ? 00000001 = interrupt 1 will initiate a dma transfer 00000000 = interrupt 0 will initiate a dma transfer bit 7 cforce: dma forced transfer bit 1 = a dma transfer is forced to begin when this bit is written to a ? 1 ? 0 = this bit always reads ? 0 ? bit 6 cabort: dma abort transfer bit 1 = a dma transfer is aborted when this bit is written to a ? 1 ? 0 = this bit always reads ? 0 ? bit 5 paten: channel pattern match abort enable bit 1 = abort transfer and clear chen on pattern match 0 = pattern match is disabled bit 4 sirqen: channel start irq enable bit 1 = start channel cell transfer if an interrupt matching chsirq occurs 0 = interrupt number chsirq is ignor ed and does not start a transfer bit 3 airqen: channel abort irq enable bit 1 = channel transfer is aborted if an interrupt matching chairq occurs 0 = interrupt number chairq is ignor ed and does not terminate a transfer bit 2-0 unimplemented: read as ? 0 ? note 1: see table 7-1: ?interrupt irq, vector and bit location? for the list of available interrupt irq sources.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 137 pic32mx330/350/370/430/450/470 register 10-9: dchxint: dma channel ?x? interrupt control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chsdie chshie chddie chdhie chb cie chccie chtaie cherie 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chsdif chshif chddif chdhif chbcif chccif chtaif cherif legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23 chsdie: channel source done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 22 chshie: channel source half empty interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 21 chddie: channel destination done interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 20 chdhie: channel destination half full interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 19 chbcie: channel block transfer complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 18 chccie: channel cell transfer complete interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 17 chtaie: channel transfer abort interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 16 cherie: channel address error interrupt enable bit 1 = interrupt is enabled 0 = interrupt is disabled bit 15-8 unimplemented: read as ? 0 ? bit 7 chsdif: channel source done interrupt flag bit 1 = channel source pointer has reached end of source (chsptr = chssiz) 0 = no interrupt is pending bit 6 chshif: channel source half empty interrupt flag bit 1 = channel source pointer has reached midp oint of source (c hsptr = chssiz/2) 0 = no interrupt is pending bit 5 chddif: channel destination done interrupt flag bit 1 = channel destination pointer has reached end of destination (chdptr = chdsiz) 0 = no interrupt is pending
pic32mx330/350/370/430/450/470 ds60001185b-page 138 preliminary ? 2012-2013 microchip technology inc. bit 4 chdhif: channel destination half full interrupt flag bit 1 = channel destination pointer has reached mi dpoint of destination (chdptr = chdsiz/2) 0 = no interrupt is pending bit 3 chbcif: channel block transfer complete interrupt flag bit 1 = a block transfer has been completed (the larger of chssiz/chdsiz bytes has been transferred), or a pattern match event occurs 0 = no interrupt is pending bit 2 chccif: channel cell transfer complete interrupt flag bit 1 = a cell transfer has been completed (chcsiz bytes have been transferred) 0 = no interrupt is pending bit 1 chtaif: channel transfer abort interrupt flag bit 1 = an interrupt matching chairq has been det ected and the dma transfer has been aborted 0 = no interrupt is pending bit 0 cherif: channel address error interrupt flag bit 1 = a channel address error has been detected ? either the source or the destination address is invalid. 0 = no interrupt is pending register 10-9: dchxint: dma channel ?x? in terrupt control register (continued)
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 139 pic32mx330/350/370/430/450/470 register 10-10: dchxssa: dma channel ?x? source start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssa<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chssa<31:0> channel source start address bits channel source start address. note: this must be the physical address of the source. register 10-11: dchxdsa: dma channel ?x? destination start address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<31:24> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<23:16> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsa<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-0 chdsa<31:0>: channel destination start address bits channel destination start address. note: this must be the physical address of the destination.
pic32mx330/350/370/430/450/470 ds60001185b-page 140 preliminary ? 2012-2013 microchip technology inc. register 10-12: dchxssiz: dma channel ?x? source size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chssiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chssiz<15:0>: channel source size bits 1111111111111111 = 65,535 byte source size ? ? ? 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size register 10-13: dchxdsiz: dma chann el ?x? destination size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chdsiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chdsiz<15:0>: channel destination size bits 1111111111111111 = 65,535 byte destination size ? ? ? 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 141 pic32mx330/350/370/430/450/470 register 10-14: dchxsptr: dma channel ?x? source pointer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chsptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chsptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chsptr<15:0>: channel source pointer bits 1111111111111111 = points to byte 65,535 of the source ? ? ? 0000000000000001 = points to byte 1 of the source 0000000000000000 = points to byte 0 of the source note 1: when in pattern detect mode, this regi ster is reset on a pattern detect. register 10-15: dchxdptr: dma channe l ?x? destination pointer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chdptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chdptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chdptr<15:0>: channel destination pointer bits 1111111111111111 = points to byte 65,535 of the destination ? ? ? 0000000000000001 = points to byte 1 of the destination 0000000000000000 = points to byte 0 of the destination
pic32mx330/350/370/430/450/470 ds60001185b-page 142 preliminary ? 2012-2013 microchip technology inc. register 10-16: dchxcsiz: dma channel ?x? cell-size register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chcsiz<15:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chcsiz<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chcsiz<15:0>: channel cell-size bits 1111111111111111 = 65,535 bytes transferred on an event ? ? ? 0000000000000010 = 2 bytes transferred on an event 0000000000000001 = 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event register 10-17: dchxcptr: dma channel ?x? cell pointer register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chcptr<15:8> 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 chcptr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 chcptr<7:0>: channel cell progress pointer bits 1111111111111111 = 65,535 bytes have been tran sferred since the last event ? ? ? 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event note 1: when in pattern detect mode, this register is reset on a pattern detect.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 143 pic32mx330/350/370/430/450/470 register 10-18: dchxdat: dma channel ?x? pattern data register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 chpdat<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 chpdat<7:0>: channel data register bits pattern terminate mode: data to be matched must be stored in this register to allow terminate on match. all other modes: unused.
pic32mx330/350/370/430/450/470 ds60001185b-page 144 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 145 pic32mx330/350/370/430/450/470 11.0 usb on-the-go (otg) the universal serial bus (usb) module contains analog and digital components to provide a usb 2.0 full-speed and low-speed embedded host, full-speed device or otg implementation with a minimum of external components. this module in host mode is intended for use as an embedded host and therefore does not implement a uhci or ohci controller. the usb module consists of the clock generator, the usb voltage comparators, the transceiver, the serial interface engine (sie), a dedicated usb dma control - ler, pull-up and pull-down resistors, and the register interface. a block diagram of the pic32 usb otg module is presented in figure 11-1 . the clock generator provides the 48 mhz clock required for usb full-speed and low-speed communi - cation. the voltage comparators monitor the voltage on the v bus pin to determine the state of the bus. the transceiver provides t he analog translation between the usb bus and the digital logic. the sie is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. the usb dma controller transfers data between the data buffers in ram and the sie. the inte - grated pull-up and pull-down resistors eliminate the need for external signaling components. the register interface allows the cpu to configure and communicate with the module. the pic32 usb module includes the following features: ? usb full-speed support for host and device ? low-speed host support ? usb otg support ? integrated signaling resistors ? integrated analog comparators for v bus monitoring ? integrated usb transceiver ? transaction handshaking performed by hardware ? endpoint buffering anywhere in system ram ? integrated dma to acce ss system ram and flash note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 27. ?usb on-the-go (otg)? (ds60001126) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. note: the implementation and use of the usb specifications, as well as other third party specifications or technologies, may require licensing; in cluding, but not limited to, usb implementers forum, inc. (also referred to as usb-if). the user is fully responsible for investigating and satisfying any applicable licensing obligations.
pic32mx330/350/370/430/450/470 ds60001185b-page 146 preliminary ? 2012-2013 microchip technology inc. figure 11-1: pic32mx430/450/470 usb interface diagram osc1 osc2 primary oscillator 8mhztypical frc oscillator tun<5:0> (4) pll 48 mhz usb clock (7) div x upllen (6) (pb out) (1) ufrcen (3) (p osc ) upllidiv (6) uf in (5) div 2 v usb 3 v 3 d+ (2) d- (2) id (8) bus transceiver sie v buson (8) comparators usb srp charge srp discharge registers and control interface transceiver power 3.3v to clock generator for core and peripherals sleep or idle sleep usben usb suspend cpu clock not p osc usb module voltage system ram usb suspend full speed pull-up host pull-down low speed pull-up host pull-down id pull-up dma note 1: pb clock is only available on th is pin for select ec modes. 2: pins can be used as digital inputs when usb is not enabled. 3: this bit field is contai ned in the osccon register. 4: this bit field is contained in the osctrm register. 5: usb pll u f in requirements: 4 mhz. 6: this bit field is contained in the devcfg2 register. 7: a 48 mhz clock is required for proper usb operation. 8: pins can be used as gpio wh en the usb module is disabled.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 147 pic32mx330/350/370/430/450/470 11.1 control registers register 11-1: u1otgir: usb otg interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs u-0 r/wc-0, hs idif t1msecif lstateif actvif sesvdif sesendif ? vbusvdif legend: wc = write ?1? to clear hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 idif: id state change indicator bit 1 = change in id state detected 0 = no change in id state detected bit 6 t1msecif: 1 millisecond timer bit 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired bit 5 lstateif: line state stable indicator bit 1 = usb line state has been stable for 1 ms, but different from last time 0 = usb line state has not been stable for 1 ms bit 4 actvif: bus activity indicator bit 1 = activity on the d+, d-, id or v bus pins has caused the device to wake-up 0 = activity has not been detected bit 3 sesvdif: session valid change indicator bit 1 =v bus voltage has dropped below the session end level 0 =v bus voltage has not dropped below the session end level bit 2 sesendif: b-device v bus change indicator bit 1 = a change on the session end input was detected 0 = no change on the session end input was detected bit 1 unimplemented: read as ? 0 ? bit 0 vbusvdif: a-device v bus change indicator bit 1 = change on the session valid input detected 0 = no change on the session valid input detected
pic32mx330/350/370/430/450/470 ds60001185b-page 148 preliminary ? 2012-2013 microchip technology inc. register 11-2: u1otgie: usb otg interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 idie t1msecie lstateie actvie sesvdie sesendie ? vbusvdie legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 idie: id interrupt enable bit 1 = id interrupt enabled 0 = id interrupt disabled bit 6 t1msecie: 1 millisecond timer interrupt enable bit 1 = 1 millisecond timer interrupt enabled 0 = 1 millisecond timer interrupt disabled bit 5 lstateie: line state interrupt enable bit 1 = line state interrupt enabled 0 = line state interrupt disabled bit 4 actvie: bus activity interrupt enable bit 1 = activity interrupt enabled 0 = activity interrupt disabled bit 3 sesvdie: session valid interrupt enable bit 1 = session valid interrupt enabled 0 = session valid interrupt disabled bit 2 sesendie: b-session end interrupt enable bit 1 = b-session end interrupt enabled 0 = b-session end interrupt disabled bit 1 unimplemented: read as ? 0 ? bit 0 vbusvdie: a-v bus valid interrupt enable bit 1 =a-v bus valid interrupt enabled 0 =a-v bus valid interrupt disabled
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 149 pic32mx330/350/370/430/450/470 register 11-3: u1otgstat: usb otg status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-0 u-0 r-0 u-0 r-0 r-0 u-0 r-0 id ?lstate ? sesvd sesend ? vbusvd legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 id: id pin state indicator bit 1 = no cable is attached or a type b cable has been plugged into the usb receptacle 0 = a ?type a? otg cable has been plugged into the usb receptacle bit 6 unimplemented: read as ? 0 ? bit 5 lstate: line state stable indicator bit 1 = usb line state (u1con and u1con) has been stable for the previous 1 ms 0 = usb line state (u1con and u1con) has not been stable for the previous 1 ms bit 4 unimplemented: read as ? 0 ? bit 3 sesvd: session valid indicator bit 1 =v bus voltage is above session valid on the a or b device 0 =v bus voltage is below session valid on the a or b device bit 2 sesend: b-device session end indicator bit 1 =v bus voltage is below session valid on the b device 0 =v bus voltage is above session valid on the b device bit 1 unimplemented: read as ? 0 ? bit 0 vbusvd: a-device v bus valid indicator bit 1 =v bus voltage is above session valid on the a device 0 =v bus voltage is below session valid on the a device
pic32mx330/350/370/430/450/470 ds60001185b-page 150 preliminary ? 2012-2013 microchip technology inc. register 11-4: u1otgcon: usb otg control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 dppulup dmpulup dppuldwn dmpuldwn vbuson otgen vbuschg vbusdis legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 dppulup: d+ pull-up enable bit 1 = d+ data line pull-up resistor is enabled 0 = d+ data line pull-up resistor is disabled bit 6 dmpulup: d- pull-up enable bit 1 = d- data line pull-up resistor is enabled 0 = d- data line pull-up resistor is disabled bit 5 dppuldwn: d+ pull-down enable bit 1 = d+ data line pull-down resistor is enabled 0 = d+ data line pull-down resistor is disabled bit 4 dmpuldwn: d- pull-down enable bit 1 = d- data line pull-down resistor is enabled 0 = d- data line pull-down resistor is disabled bit 3 vbuson: v bus power-on bit 1 =v bus line is powered 0 =v bus line is not powered bit 2 otgen: otg functionality enable bit 1 = dppulup, dmpulup, dppuldwn and dmpuldwn bits are under software control 0 = dppulup, dmpulup, dppuldwn and dmpuldwn bits are under usb hardware control bit 1 vbuschg: v bus charge enable bit 1 =v bus line is charged through a pull-up resistor 0 =v bus line is not charged through a resistor bit 0 vbusdis: v bus discharge enable bit 1 =v bus line is discharged through a pull-down resistor 0 =v bus line is not discharged through a resistor
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 151 pic32mx330/350/370/430/450/470 register 11-5: u1pwrc: usb power control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-0 u-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 uactpnd ? ? uslpgrd usbbusy ? ususpend usbpwr legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 uactpnd: usb activity pending bit 1 = usb bus activity has been detected; but an interrupt is pending, it has not been generated yet 0 = an interrupt is not pending bit 6-5 unimplemented: read as ? 0 ? bit 4 uslpgrd: usb sleep entry guard bit 1 = sleep entry is blocked if usb bus activity is detected or if a notification is pending 0 = usb module does not block sleep entry bit 3 usbbusy: usb module busy bit (1) 1 = usb module is active or disabled, but not ready to be enabled 0 = usb module is not active and is ready to be enabled note: when usbpwr = 0 and usbbusy = 1 , status from all other registers is invalid and writes to all usb module registers produce undefined results. bit 2 unimplemented: read as ? 0 ? bit 1 ususpend: usb suspend mode bit 1 = usb module is placed in suspend mode ? (the 48 mhz usb clock will be gated off. the tr ansceiver is placed in a low-power state.) 0 = usb module operates normally bit 0 usbpwr: usb operation enable bit 1 = usb module is turned on 0 = usb module is disabled ? (outputs held inactive, device pins not used by usb, analog features are shut down to reduce power consumption.)
pic32mx330/350/370/430/450/470 ds60001185b-page 152 preliminary ? 2012-2013 microchip technology inc. register 11-6: u1ir: usb interrupt register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r-0 r/wc-0, hs stallif attachif (1) resumeif (2) idleif trnif (3) sofif uerrif (4) urstif (5) detachif (6) legend: wc = write ?1? to clear hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 stallif: stall handshake interrupt bit 1 = in host mode a stall handshake was received during the handshake phase of the transaction in device mode a stall handshake was transmitte d during the handshake phase of the transaction 0 = stall handshake has not been sent bit 6 attachif: peripheral attach interrupt bit (1) 1 = peripheral attachment was detected by the usb module 0 = peripheral attachment was not detected bit 5 resumeif: resume interrupt bit (2) 1 = k-state is observed on the d+ or d- pin for 2.5 s 0 = k-state is not observed bit 4 idleif: idle detect interrupt bit 1 = idle condition detected (constant idle state of 3 ms or more) 0 = no idle condition detected bit 3 trnif: token processing complete interrupt bit (3) 1 = processing of current token is complete; a read of the u1stat register will provide endpoint information 0 = processing of current token not complete bit 2 sofif: sof token interrupt bit 1 = sof token received by the peripheral or the sof threshold reached by the host 0 = sof token was not received nor threshold reached bit 1 uerrif: usb error condition interrupt bit (4) 1 = unmasked error condition has occurred 0 = unmasked error condition has not occurred bit 0 urstif: usb reset interrupt bit (device mode) (5) 1 = valid usb reset has occurred 0 = no usb reset has occurred bit 0 detachif: usb detach interrupt bit (host mode) (6) 1 = peripheral detachment was detected by the usb module 0 = peripheral detachment was not detected note 1: this bit is valid only if the hosten bit is set (see register 11-11 ), there is no activity on the usb for 2.5 s, and the current bus state is not se0. 2: when not in suspend mode, this interrupt should be disabled. 3: clearing this bit will cause the stat fifo to advance. 4: only error conditions enabled through the u1eie register will set this bit. 5: device mode. 6: host mode.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 153 pic32mx330/350/370/430/450/470 register 11-7: u1ie: usb interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stallie attachie resumeie idleie trnie sofie uerrie (1) urstie (2) detachie (3) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 stallie: stall handshake interrupt enable bit 1 = stall interrupt enabled 0 = stall interrupt disabled bit 6 attachie: attach interrupt enable bit 1 = attach interrupt enabled 0 = attach interrupt disabled bit 5 resumeie: resume interrupt enable bit 1 = resume interrupt enabled 0 = resume interrupt disabled bit 4 idleie: idle detect interrupt enable bit 1 = idle interrupt enabled 0 = idle interrupt disabled bit 3 trnie: token processing complete interrupt enable bit 1 = trnif interrupt enabled 0 = trnif interrupt disabled bit 2 sofie: sof token interrupt enable bit 1 = sofif interrupt enabled 0 = sofif interrupt disabled bit 1 uerrie: usb error interrupt enable bit (1) 1 = usb error interrupt enabled 0 = usb error interrupt disabled bit 0 urstie: usb reset interrupt enable bit (2) 1 = urstif interrupt enabled 0 = urstif interrupt disabled detachie: usb detach interrupt enable bit (3) 1 = dattchif interrupt enabled 0 = dattchif interrupt disabled note 1: for an interrupt to propagate usbif, the uerrie bit (u1ie<1>) must be set. 2: device mode. 3: host mode.
pic32mx330/350/370/430/450/470 ds60001185b-page 154 preliminary ? 2012-2013 microchip technology inc. register 11-8: u1eir: usb error interrupt status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs r/wc-0, hs btsef bmxef dmaef (1) btoef (2) dfn8ef crc16ef crc5ef (4) pidef eofef (3,5) legend: wc = write ?1? to clear hs = hardware settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 btsef: bit stuff error flag bit 1 = packet rejected due to bit stuff error 0 = packet accepted bit 6 bmxef: bus matrix error flag bit 1 = the base address, of the bdt, or the address of an individual buffer pointed to by a bdt entry, is invalid. 0 = no address error bit 5 dmaef: dma error flag bit (1) 1 = usb dma error condition detected 0 =no dma error bit 4 btoef: bus turnaround time-out error flag bit (2) 1 = bus turnaround time-out has occurred 0 = no bus turnaround time-out bit 3 dfn8ef: data field size error flag bit 1 = data field received is not an integral number of bytes 0 = data field received is an integral number of bytes bit 2 crc16ef: crc16 failure flag bit 1 = data packet rejected due to crc16 error 0 = data packet accepted note 1: this type of error occurs when the module?s request fo r the dma bus is not granted in time to service the module?s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the receiv ed data packet causing it to be truncated. 2: this type of error occurs when more than 16-bit-tim es of idle from the previous end-of-packet (eop) has elapsed. 3: this type of error occurs when the module is tran smitting or receiving data and the sof counter has reached zero. 4: device mode. 5: host mode.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 155 pic32mx330/350/370/430/450/470 bit 1 crc5ef: crc5 host error flag bit (4) 1 = token packet rejected due to crc5 error 0 = token packet accepted eofef: eof error flag bit (3,5) 1 = eof error condition detected 0 = no eof error condition bit 0 pidef: pid check failure flag bit 1 = pid check failed 0 = pid check passed register 11-8: u1eir: usb error interrupt status register (continued) note 1: this type of error occurs when the module?s request fo r the dma bus is not granted in time to service the module?s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the receiv ed data packet causing it to be truncated. 2: this type of error occurs when more than 16-bit-tim es of idle from the previous end-of-packet (eop) has elapsed. 3: this type of error occurs when the module is tran smitting or receiving data and the sof counter has reached zero. 4: device mode. 5: host mode.
pic32mx330/350/370/430/450/470 ds60001185b-page 156 preliminary ? 2012-2013 microchip technology inc. register 11-9: u1eie: usb error interrupt enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 btsee bmxee dmaee btoee dfn8ee crc16ee crc5ee (1) pidee eofee (2) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 btsee: bit stuff error interrupt enable bit 1 = btsef interrupt enabled 0 = btsef interrupt disabled bit 6 bmxee: bus matrix error interrupt enable bit 1 = bmxef interrupt enabled 0 = bmxef interrupt disabled bit 5 dmaee: dma error interrupt enable bit 1 = dmaef interrupt enabled 0 = dmaef interrupt disabled bit 4 btoee: bus turnaround time-out error interrupt enable bit 1 = btoef interrupt enabled 0 = btoef interrupt disabled bit 3 dfn8ee: data field size erro r interrupt enable bit 1 = dfn8ef interrupt enabled 0 = dfn8ef interrupt disabled bit 2 crc16ee: crc16 failure interrupt enable bit 1 = crc16ef interrupt enabled 0 = crc16ef interrupt disabled bit 1 crc5ee: crc5 host error interrupt enable bit (1) 1 = crc5ef interrupt enabled 0 = crc5ef interrupt disabled eofee: eof error interrupt enable bit (2) 1 = eof interrupt enabled 0 = eof interrupt disabled bit 0 pidee: pid check failure interrupt enable bit 1 = pidef interrupt enabled 0 = pidef interrupt disabled note 1: device mode. 2: host mode. note: for an interrupt to propagate usbif, the uerrie bit (u1ie<1>) must be set.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 157 pic32mx330/350/370/430/450/470 register 11-10: u1stat: usb status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-x r-x r-x r-x r-x r-x u-0 u-0 endpt<3:0> dir ppbi ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-4 endpt<3:0>: encoded number of last endpoint activity bits ? (represents the number of the bdt, updated by the last usb transfer.) 1111 = endpoint 15 1110 = endpoint 14 ? ? ? 0001 =endpoint 1 0000 =endpoint 0 bit 3 dir: last bd direction indicator bit 1 = last transaction was a transmit transfer (tx) 0 = last transaction was a receive transfer (rx) bit 2 ppbi: ping-pong bd pointer indicator bit 1 = the last transaction was to the odd bd bank 0 = the last transaction was to the even bd bank bit 1-0 unimplemented: read as ? 0 ? note: the u1stat register is a window into a 4-byte fifo maintained by the usb module. u1stat value is only valid when u1ir is active. clearing the u1ir bit advances the fifo. data in register is invalid when u1ir = 0 .
pic32mx330/350/370/430/450/470 ds60001185b-page 158 preliminary ? 2012-2013 microchip technology inc. register 11-11: u1con: usb control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-x r-x r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 jstate se0 pktdis (4) usbrst hosten (2) resume (3) ppbrst usben (4) tokbusy (1,5) sofen (5) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 jstate: live differential receiver jstate flag bit 1 = jstate detected on the usb 0 = no jstate detected bit 6 se0: live single-ended zero flag bit 1 = single ended zero detected on the usb 0 = no single ended zero detected bit 5 pktdis: packet transfer disable bit (4) 1 = token and packet processing disabled (set upon setup token received) 0 = token and packet processing enabled tokbusy: token busy indicator bit (1,5) 1 = token being executed by the usb module 0 = no token being executed bit 4 usbrst: module reset bit (5) 1 = usb reset generated 0 = usb reset terminated bit 3 hosten: host mode enable bit (2) 1 = usb host capability enabled 0 = usb host capability disabled bit 2 resume: resume signaling enable bit (3) 1 = resume signaling activated 0 = resume signaling disabled note 1: software is required to check this bit before issu ing another token command to the u1tok register (see register 11-15 ). 2: all host control logic is reset any time that the value of this bit is toggled. 3: software must set the resume bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. in host mode, the usb module will append a low-speed eop to the resume signaling when this bit is cleared. 4: device mode. 5: host mode.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 159 pic32mx330/350/370/430/450/470 bit 1 ppbrst: ping-pong buffers reset bit 1 = reset all even/odd buffer pointers to the even bd banks 0 = even/odd buffer pointers not being reset bit 0 usben: usb module enable bit (4) 1 = usb module and supporting circuitry enabled 0 = usb module and supporting circuitry disabled sofen: sof enable bit (5) 1 = sof token sent every 1 ms 0 = sof token disabled register 11-11: u1con: usb control register (continued) note 1: software is required to check this bit before issu ing another token command to the u1tok register (see register 11-15 ). 2: all host control logic is reset any time that the value of this bit is toggled. 3: software must set the resume bit for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. in host mode, the usb module will append a low-speed eop to the resume signaling when this bit is cleared. 4: device mode. 5: host mode.
pic32mx330/350/370/430/450/470 ds60001185b-page 160 preliminary ? 2012-2013 microchip technology inc. register 11-12: u1addr: usb address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspden devaddr<6:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 lspden: low speed enable indicator bit 1 = next token command to be executed at low speed 0 = next token command to be executed at full speed bit 6-0 devaddr<6:0>: 7-bit usb device address bits register 11-13: u1frml: usb frame number low register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 frml<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 frml<7:0>: the 11-bit frame number lower bits the register bits are updated with the current fr ame number whenever a sof token is received.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 161 pic32mx330/350/370/430/450/470 register 11-14: u1frmh: usb frame number high register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 r-0 r-0 r-0 ? ? ? ? ? frmh<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-3 unimplemented: read as ? 0 ? bit 2-0 frmh<2:0>: the upper 3 bits of the frame numbers bits the register bits are updated with the current fr ame number whenever a sof token is received. register 11-15: u1tok: usb token register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pid<3:0> (1) ep<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-4 pid<3:0>: token type indicator bits (1) 0001 = out (tx) token type transaction 1001 = in (rx) token type transaction 1101 = setup (tx) token type transaction note: all other values are rese rved and must not be used. bit 3-0 ep<3:0>: token command endpoint address bits the four bit value must specify a valid endpoint. note 1: all other values are rese rved and must not be used.
pic32mx330/350/370/430/450/470 ds60001185b-page 162 preliminary ? 2012-2013 microchip technology inc. register 11-16: u1sof: us b sof threshold register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cnt<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 cnt<7:0>: sof threshold value bits typical values of the threshold are: 01001010 = 64-byte packet 00101010 = 32-byte packet 00011010 = 16-byte packet 00010010 = 8-byte packet register 11-17: u1bdtp1: usb bdt page 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 bdtptrl<15:9> ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-1 bdtptrl<15:9>: bdt base address bits this 7-bit value provides address bits 15 through 9 of the bdt base address, which defines the starting location of the bdt in system memory. the 32-bit bdt base address is 512-byte aligned. bit 0 unimplemented: read as ? 0 ?
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 163 pic32mx330/350/370/430/450/470 register 11-18: u1bdtp2: usb bdt page 2 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdtptrh<23:16> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 bdtptrh<23:16>: bdt base address bits this 8-bit value provides address bits 23 through 16 of the bdt base address, which defines the starting location of the bdt in system memory. the 32-bit bdt base address is 512-byte aligned. register 11-19: u1bdtp3: usb bdt page 3 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bdtptru<31:24> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7-0 bdtptru<31:24>: bdt base address bits this 8-bit value provides address bits 31 through 24 of the bdt base address, defines the starting location of the bdt in system memory. the 32-bit bdt base address is 512-byte aligned.
pic32mx330/350/370/430/450/470 ds60001185b-page 164 preliminary ? 2012-2013 microchip technology inc. register 11-20: u1cnfg1: usb configuration 1 register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 uteye uoemon ? usbsidl ? ? ? uasuspnd legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 uteye: usb eye-pattern test enable bit 1 = eye-pattern test enabled 0 = eye-pattern test disabled bit 6 uoemon: usb oe monitor enable bit 1 = oe signal active; it indicates intervals during which the d+/d- lines are driving 0 = oe signal inactive bit 5 unimplemented: read as ? 0 ? bit 4 usbsidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 3-1 unimplemented: read as ? 0 ? bit 0 uasuspnd: automatic suspend enable bit 1 = usb module automatically suspends upon entry to sleep mode. see the ususpend bit (u1pwrc<1>) in register 11-5 . 0 = usb module does not automatically suspend upon entry to sleep mode. software must use the ususpend bit (u1pwrc<1>) to suspend the module, including the usb 48 mhz clock
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 165 pic32mx330/350/370/430/450/470 register 11-21: u1ep0-u1ep15: us b endpoint control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 lspd retrydis ? epcondis eprxen eptxen epstall ephshk legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-8 unimplemented: read as ? 0 ? bit 7 lspd: low-speed direct connection enable bit (host mode and u1ep0 only) 1 = direct connection to a low-speed device enabled 0 = direct connection to a low-speed device disabled; hub required with pre_pid bit 6 retrydis: retry disable bit (host mode and u1ep0 only) 1 = retry nak?d transactions disabled 0 = retry nak?d transactions enabled; retry done in hardware bit 5 unimplemented: read as ? 0 ? bit 4 epcondis: bidirectional endpoint control bit if eptxen = 1 and eprxen = 1 : 1 = disable endpoint n from control transfers; only tx and rx transfers allowed 0 = enable endpoint n for control (setup) transfers; tx and rx transfers also allowed otherwise, this bit is ignored. bit 3 eprxen: endpoint receive enable bit 1 = endpoint n receive enabled 0 = endpoint n receive disabled bit 2 eptxen: endpoint transmit enable bit 1 = endpoint n transmit enabled 0 = endpoint n transmit disabled bit 1 epstall: endpoint stall status bit 1 = endpoint n was stalled 0 = endpoint n was not stalled bit 0 ephshk: endpoint handshake enable bit 1 = endpoint handshake enabled 0 = endpoint handshake disabled (typically used for isochronous endpoints)
pic32mx330/350/370/430/450/470 ds60001185b-page 166 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 167 pic32mx330/350/370/430/450/470 12.0 i/o ports general purpose i/o pins ar e the simplest of peripher - als. they allow the pic ? mcu to monitor and control other devices. to add flexibilit y and functionality, some pins are multiplexed with alternate function(s). these functions depend on which peripheral features are on the device. in general, when a peripheral is functioning, that pin may not be used as a general purpose i/o pin. following are some of the key features of this module: ? individual output pin open-drain enable/disable ? individual input pin weak pull-up and pull-down ? monitor selective inputs and generate interrupt when change in pin state is detected ? operation during cpu sleep and idle modes ? fast bit manipulation using clr, set and inv registers figure 12-1 illustrates a block diagram of a typical multiplexed i/o port. figure 12-1: block diagram of a typical multiplexed port structure note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 12. ?i/o ports? (ds60001120) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. peripheral output data peripheral module peripheral output enable pio module peripheral module enable wr lat i/o pin wr port data bus rd lat rd port rd tris wr tris 0 1 rd odc sysclk q d ck en q q d ck en q q d ck en q q d ck q q d ck q 0 1 sysclk wr odc odc tris lat sleep 1 0 1 0 output multiplexers i/o cell synchronization r peripheral input legend: r = peripheral input buffer types may vary. refer to table 1-1 for peripheral details. note: this block diagram is a general representation of a shared port/ peripheral structure for illustration purposes only. the actual structure for any specific port/peripheral combination may be different than it is shown here. peripheral input buffer
pic32mx330/350/370/430/450/470 ds60001185b-page 168 preliminary ? 2012-2013 microchip technology inc. 12.1 parallel i/o (pio) ports all port pins have ten regi sters directly associated with their operation as digital i/o. the data direction register (trisx) determines whether t he pin is an input or an output. if the data direction bit is a ? 1 ?, then the pin is an input. all port pins are defined as inputs after a reset. reads from the latch (latx) read the latch. writes to the latch write the latch. reads from the port (portx) read the port pins, while writes to the port pins write the latch. 12.1.1 open-drain configuration in addition to the portx, latx, and trisx registers for data control, some port pins can also be individually configured for either digital or open-drain output. this is controlled by the open-drain control register, odcx, associated with each port. setting any of the bits con - figures the corresponding pin to act as an open-drain output. the open-drain feature al lows the generation of out - puts higher than v dd (e.g., 5v) on any desired 5v-tol - erant pins by using external pull-up resistors. the maximum open-drain voltage allowed is the same as the maximum v ih specification. see the ? pin diagrams ? section for the available pins and their functionality. 12.1.2 configuring analog and digital port pins the anselx register controls the operation of the analog port pins. the port pins that are to function as analog inputs must have their corresponding ansel and tris bits set. in order to use port pins for i/o functionality with digital modules, such as timers, uarts, etc., the corresponding anselx bit must be cleared. the anselx register has a default value of 0xffff; therefore, all pins that share analog functions are analog (not digital) by default. if the tris bit is cleared (output) while the anselx bit is set, the digital output level (v oh or v ol ) is converted by an analog peripheral, such as the adc module or comparator module. when the port register is read, all pins configured as analog input channels are read as cleared (a low level). pins configured as digital inputs do not convert an analog input. analog levels on any pin defined as a digital input (including the anx pins) can cause the input buffer to consume current that exceeds the device specifications. 12.1.3 i/o port write/read timing one instruction cycle is required between a port direction change or port write operation and a read operation of the same port. typically this instruction would be an nop . 12.1.4 input change notification the input change notification function of the i/o ports allows the pic32mx330/ 350/370/430/450/470 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. this feature can detect input change-of-states even in sleep mode, when th e clocks are disabled. every i/o port pin can be selected (enabled) for generating an interrupt request on a change-of-state. five control registers are associated with the cn func - tionality of each i/o port. the cnenx registers contain the cn interrupt enable control bits for each of the input pins. setting any of these bits enables a cn interrupt for the corresponding pins. the cnstatx register indicates whether a change occurred on the corresponding pin since the last read of the portx bit. each i/o pin also has a weak pull-up and every i/o pin has a weak pull-down connected to it. the pull- ups act as a current source or sink source connected to the pin, and eliminate the need for external resistors when push-button or keypad devices are connected. the pull-ups and pull-downs are enabled separately using the cnpux and the cnpdx registers, which contain the control bits for each of the pins. setting any of the cont rol bits enables the weak pull-ups and/or pull-downs for the corresponding pins. an additional control regist er (cnconx) is shown in register 12-3 . 12.2 clr, set, and inv registers every i/o module register has a corresponding clr (clear), set (set) and inv (invert) register designed to provide fast atomic bit manipulations. as the name of the register implies, a valu e written to a set, clr or inv register effectively performs the implied operation, but only on the corresponding base register and only bits specified as ? 1 ? are modified. bits specified as ? 0 ? are not modified. reading set, clr and inv registers returns undefined values. to see the affects of a write operation to a set, clr or inv register, the base register must be read. note: pull-ups and pull-downs on change notifi- cation pins should always be disabled when the port pin is configured as a digital output.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 169 pic32mx330/350/370/430/450/470 12.3 peripheral pin select a major challenge in general purpose devices is provid - ing the largest possible set of peripheral features while minimizing the conflict of features on i/o pins. the chal - lenge is even greater on low pin-count devices. in an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. peripheral pin select configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of i/o pins. by increasing the pinout options available on a particular device, users can be tter tailor the device to their entire application, rather than trimming the application to fit the device. the peripheral pin select configuration feature oper - ates over a fixed subset of digital i/o pins. users may independently map the input an d/or output of most dig - ital peripherals to these i/o pins. peripheral pin select is performed in software and generally does not require the device to be reprogrammed. hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 12.3.1 available pins the number of available pins is dependent on the particular device and its pin co unt. pins that support the peripheral pin select feat ure include the designation ?rpn? in their full pin designation, where ?rp? designates a remappable peripheral and ?n? is the remappable port number. 12.3.2 available peripherals the peripherals managed by the peripheral pin select are all digital-only peripherals. these include general serial communications (uart and spi), general pur - pose timer clock inputs, time r-related peripherals (input capture and output compare) and interrupt-on-change inputs. in comparison, some digital-only peripheral modules are never included in the peri pheral pin sele ct feature. this is because the peripheral?s function requires spe - cial i/o circuitry on a specific port and cannot be easily connected to multiple pins. these modules include i 2 c among others. a similar requirement excludes all mod - ules with analog inputs, such as the analog-to-digital converter (adc). a key difference between remappable and non-remap - pable peripherals is that remappable peripherals are not associated with a default i/o pin. the peripheral must always be assigned to a specific i/o pin before it can be used. in contrast, non-remappable peripherals are always available on a defau lt pin, assuming that the peripheral is active and not conflicting with another peripheral. when a remappable peripheral is active on a given i/o pin, it takes priority over all other digital i/o and digital communication peripherals associated with the pin. priority is given regardless of the type of peripheral that is mapped. remappable peripherals never take priority over any analog functions associated with the pin. 12.3.3 controlling peripheral pin select peripheral pin select features are controlled through two sets of sfrs: one to map peripheral inputs, and one to map outputs. because they are separately con - trolled, a particular peripher al?s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. the association of a peripheral to a peripheral-select - able pin is handled in two different ways, depending on whether an input or output is being mapped. 12.3.4 input mapping the inputs of the peripheral pin select options are mapped on the basis of the peripheral. that is, a control register associated with a peripheral dictates the pin it will be mapped to. the [ pin name ] r registers, where [ pin name ] refers to the peripheral pins listed in table 12-1 , are used to configure peripheral input mapping (see register 12-1 ). each register contains sets of 4 bit fields. programming these bit fields with an appropriate value maps the rpn pin with the corresponding value to that peripheral. for any given device, the valid range of values for any bit field is shown in ta b l e 12-1 . for example, figure 12-2 illustrates the remappable pin selection for the u1rx input. figure 12-2: remappable input example for u1rx rpa2 rpb6 rpa4 0 1 2 u1rx input u1rxr<3:0> to peripheral rpn n note: for input only, peripheral pin select functionality does not have priority over trisx settings. therefore, when configuring rpn pin for input, the corresponding bit in the trisx register must also be configured for input (set to ? 1 ?).
pic32mx330/350/370/430/450/470 ds60001185b-page 170 preliminary ? 2012-2013 microchip technology inc. table 12-1: input pin selection peripheral pin [ pin name ]r sfr [ pin name ]r bits [ pin name ]r value to rpn pin selection int3 int3r int3r<3:0> 0000 = rpd2 0001 = rpg8 0010 = rpf4 0011 = rpd10 0100 = rpf1 0101 = rpb9 0110 = rpb10 0111 = rpc14 1000 = rpb5 1001 = reserved 1010 = rpc1 (3) 1011 = rpd14 (3) 1100 = rpg1 (3) 1101 = rpa14 (3) 1110 = reserved 1111 = rpf2 (1) t2ck t2ckr t2ckr<3:0> ic3 ic3r ic3r<3:0> u1rx u1rxr u1rxr<3:0> u2rx u2rxr u2rxr<3:0> u5cts u5ctsr u5ctsr<3:0> refclki refclkir refclkir<3:0> int4 int4r int4r<3:0> 0000 = rpd3 0001 = rpg7 0010 = rpf5 0011 = rpd11 0100 = rpf0 0101 = rpb1 0110 = rpe5 0111 = rpc13 1000 = rpb3 1001 = reserved 1010 = rpc4 (3) 1011 = rpd15 (3) 1100 = rpg0 (3) 1101 = rpa15 (3) 1110 = rpf2 (1) 1111 = rpf7 (2) t5ck t5ckr t5ckr<3:0> ic4 ic4r ic4r<3:0> u3rx u3rxr u3rxr<3:0> u4cts u4ctsr u4ctsr<3:0> sdi1 sdi1r sdi1r<3:0> sdi2 sdi2r sdi2r<3:0> int2 int2r int2r<3:0> 0000 = rpd9 0001 = rpg6 0010 = rpb8 0011 = rpb15 0100 = rpd4 0101 = rpb0 0110 = rpe3 0111 = rpb7 1000 = reserved 1001 = rpf12 (3) 1010 = rpd12 (3) 1011 = rpf8 (3) 1100 = rpc3 (3) 1101 = rpe9 (3) 1110 = reserved 1111 = rpb2 t4ck t4ckr t4ckr<3:0> ic2 ic2r ic2r<3:0> ic5 ic5r ic5r<3:0> u1cts u1ctsr u2ctsr<3:0> u2cts u2ctsr u2ctsr<3:0> ss1 ss1r ss1r<3:0> note 1: this selection is not available on 64-pin usb devices. 2: this selection is only available on 100-pin general purpose devices. 3: this selection is not available on 64- pin usb and general purpose devices.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 171 pic32mx330/350/370/430/450/470 int1 int1r int1r<3:0> 0000 = rpd1 0001 = rpg9 0010 = rpb14 0011 = rpd0 0100 = rpd8 0101 = rpb6 0110 = rpd5 0111 = rpb2 1000 = rpf3 (2) 1001 = rpf13 (3) 1010 = reserved 1011 = rpf2 (1) 1100 = rpc2 1101 = rpe8 (3) 1110 = reserved 1111 = reserved t3ck t3ckr t3ckr<3:0> ic1 ic1r ic1r<3:0> u3cts u3ctsr u3ctsr<3:0> u4rx u4rxr u4rxr<3:0> u5rx u5rxr u5rxr<3:0> ss2 ss2r ss2r<3:0> ocfa ocfar ocfar<3:0> table 12-1: input pin selection (continued) peripheral pin [ pin name ]r sfr [ pin name ]r bits [ pin name ]r value to rpn pin selection note 1: this selection is not available on 64-pin usb devices. 2: this selection is only available on 100-pin general purpose devices. 3: this selection is not available on 64- pin usb and general purpose devices.
pic32mx330/350/370/430/450/470 ds60001185b-page 172 preliminary ? 2012-2013 microchip technology inc. 12.3.5 output mapping in contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. in this case, a control regi ster associated with a particular pin dictates the peripheral output to be mapped. the rpnr registers ( register 12-2 ) are used to control output mapping. like the [ pin name ]r registers, each register cont ains sets of 4 bit fields. the value of the bit field corresponds to one of the peripherals, and that peripheral?s output is mapped to the pin (see table 12-2 and figure 12-3 ). a null output is associated wit h the output register reset value of ? 0 ?. this is done to ensure that remappable outputs remain disconnected from all output pins by default. figure 12-3: example of multiplexing of remappable output for rpa0 12.3.6 controllin g configuration changes because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. pic32 devices include two features to prevent alterations to the peripheral map: ? control register lock sequence ? configuration bit select lock 12.3.6.1 control register lock under normal operation, writes to the rpnr and [ pin name ]r registers are not allowed. attempted writes appear to execute normally, but the contents of the registers remain unchanged. to change these regis - ters, they must be unlocked in hardware. the regis - ter lock is controlled by the iolock configuration bit (cfgcon<13>). setting iolock prevents writes to the control registers; clear ing iolock allows writes. to set or clear the iolock bit, an unlock sequence must be executed. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details. 12.3.6.2 configuration bit select lock as an additional level of safety, the device can be configured to prevent more than one write session to the rpnr and [ pin name ]r registers. the iol1way configuration bit (devcfg3<29>) blocks the iolock bit from being cleared after it has been set once. if iolock remains set, the register unlock procedure does not execute, and the pe ripheral pin select control registers cannot be written to. the only way to clear the bit and re-enable peripheral remapping is to perform a device reset. in the default (unprogrammed) state, iol1way is set, restricting users to one write session. rpa0r<3:0> 0 15 1 default u1tx output u1rts output 2 14 output data rpa0
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 173 pic32mx330/350/370/430/450/470 table 12-2: output pin selection rpn port pin rpnr sfr rpnr bits rpnr value to peripheral selection group 1 selections rpd2 rpd2r rpd2r<3:0> 0000 = no connect 0001 = u3tx 0010 = u4rts 0011 = reserved 0100 = reserved 0101 = reserved 0110 = sdo2 0111 = reserved 1000 = reserved 1001 = reserved 1010 = reserved 1011 = oc3 1100 = reserved 1101 = c2out 1110 = reserved 1111 = reserved rpg8 rpg8r rpg8r<3:0> rpf4 rpf4r rpf4r<3:0> rpd10 rpd10r rpd10r<3:0> rpf1 rpf1r rpf1r<3:0> rpb9 rpb9r rpb9r<3:0> rpb10 rpb10r rpb10r<3:0> rpc14 rpc14r rpc14r<3:0> rpb5 rpb5r rpb5r<3:0> rpc1 (4) rpc1r rpc1r<3:0> rpd14 (5) rpd14r rpd14r<3:0> rpg1 (4) rpg1r rpg1r<3:0> rpa14 (4) rpa14r rpa14r<3:0> rpd3 rpd3r rpd3r<3:0> 0000 = no connect 0001 = u2tx 0010 = reserved 0011 = u1tx 0100 = u5rts 0101 = reserved 0110 = sdo2 0111 = reserved 1000 = sdo1 1001 = reserved 1010 = reserved 1011 = oc4 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved rpg7 rpg7r rpg7r<3:0> rpf5 rpf5r rpf5r<3:0> rpd11 rpd11r rpd11r<3:0> rpf0 rpf0r rpf0r<3:0> rpb1 rpb1r rpb1r<3:0> rpe5 rpe5r rpe5r<3:0> rpc13 rpc13r rpc13r<3:0> rpb3 rpb3r rpb3r<3:0> rpf3 (2) rpf3r rpf3r<3:0> rpc4 (4) rpc4r rpc4r<3:0> rpd15 (5) rpd15r rpd15r<3:0> rpg0 (4) rpg0r rpg0r<3:0> rpa15 (4) rpa15r rpa15r<3:0> note 1: this selection is not available on usb devices. 2: this selection is only available on 64-pin general purpose devices. 3: this selection is only available on 100-pin general purpose devices. 4: this selection is only available on 100-pin usb and general purpose devices. 5: this selection is not available on 64-pin usb devices.
pic32mx330/350/370/430/450/470 ds60001185b-page 174 preliminary ? 2012-2013 microchip technology inc. rpd9 rpd9r rpd9r<3:0> 0000 = no connect 0001 = u3rts 0010 = u4tx 0011 = refclko 0100 = u5tx 0101 = reserved 0110 = reserved 0111 = ss1 1000 = sdo1 1001 = reserved 1010 = reserved 1011 = oc5 1100 = reserved 1101 = c1out 1110 = reserved 1111 = reserved rpg6 rpg6r rpg6r<3:0> rpb8 rpb8r rpb8r<3:0> rpb15 rpb15r rpb15r<3:0> rpd4 rpd4r rpd4r<3:0> rpb0 rpb0r rpb0r<3:0> rpe3 rpe3r rpe3r<3:0> rpb7 rpb7r rpb7r<3:0> rpb2 rpb2r rpb2r<3:0> rpf12 (4) rpf12r rpf12r<3:0> rpd12 (4) rpd12r rpd12r<3:0> rpf8 (5) rpf8r rpf8r<3:0> rpc3 (4) rpc3r rpc3r<3:0> rpe9 (4) rpe9r rpe9r<3:0> rpd1 rpd1r rpd1r<3:0> 0000 = no connect 0001 = u2rts 0010 = reserved 0011 = u1rts 0100 = u5tx 0101 = reserved 0110 = ss2 0111 = reserved 1000 = sdo1 1001 = reserved 1010 = reserved 1011 = oc2 1100 = oc1 1101 = reserved 1110 = reserved 1111 = reserved rpg9 rpg9r rpg9r<3:0> rpb14 rpb14r rpb14r<3:0> rpd0 rpd0r rpd0r<3:0> rpd8 rpd8r rpd8r<3:0> rpb6 rpb6r rpb6r<3:0> rpd5 rpd5r rpd5r<3:0> rpf3 (3) rpf3r rpf3r<3:0> rpf6 (1) rpf6r rpf6r<3:0> rpf13 (4) rpf13r rpf13r<3:0> rpc2 (4) rpc2r rpc2r<3:0> rpe8 (4) rpe8r rpe8r<3:0> rpf2 (5) rpf2r rpf2r<3:0> table 12-2: output pin selection (continued) rpn port pin rpnr sfr rpnr bits rpnr value to peripheral selection note 1: this selection is not available on usb devices. 2: this selection is only available on 64-pin general purpose devices. 3: this selection is only available on 100-pin general purpose devices. 4: this selection is only available on 100-pin usb and general purpose devices. 5: this selection is not available on 64-pin usb devices.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 175 pic32mx330/350/370/430/450/470 12.4 control registers register 12-1: [ pin name ]r: peripheral pin sel ect input register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ?[ pin name ]r<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as ? 0 ? bit 3-0 [ pin name ]r<3:0>: peripheral pin select input bits where [ pin name ] refers to the pins that are used to configure peripheral input mapping. see table 12-1 for input pin selection values. note: register values can only be changed if t he iolock configuration bit (cfgcon<13>) = 0 . register 12-2: rpnr: periphera l pin select output register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ?rpnr<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-4 unimplemented: read as ? 0 ? bit 3-0 rpnr<3:0>: peripheral pin select output bits see table 12-2 for output pin selection values. note: register values can only be changed if t he iolock configuration bit (cfgcon<13>) = 0 .
pic32mx330/350/370/430/450/470 ds60001185b-page 176 preliminary ? 2012-2013 microchip technology inc. register 12-3: cnconx: change notice co ntrol for portx register (x = a ? g) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on ?sidl ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: change notice (cn) control on bit 1 = cn is enabled 0 = cn is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle control bit 1 = cpu idle mode halts cn operation 0 = cpu idle does not affect cn operation bit 12-0 unimplemented: read as ? 0 ?
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 177 pic32mx330/350/370/430/450/470 13.0 timer1 this family of pic32 devices features one synchronous/ asynchronous 16-bit timer that can operate as a free-run - ning interval timer for various timing applications and counting external events. this timer can also be used with the low-power secondary oscillator (s osc ) for real-time clock (rtc) applications. the following modes are supported: ? synchronous internal timer ? synchronous internal gated timer ? synchronous external timer ? asynchronous external timer 13.1 additional supported features ? selectable clock prescaler ? timer operation during cpu idle and sleep mode ? fast bit manipulation using clr, set and inv registers ? asynchronous mode can be used with the s osc to function as a real-time clock (rtc) figure 13-1: timer1 block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. ?timers? (ds60001105) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. on sync sosci sosco/t1ck pr1 t1if equal 16-bit comparator tmr1 reset soscen (1) event flag 1 0 tsync tgate tgate pbclk 1 0 tcs gate sync tckps<1:0> prescaler 2 1, 8, 64, 256 x 1 1 0 0 0 q q d note 1: the default state of the soscen bit (osccon<1>) duri ng a device reset is controlled by the fsoscen bit in configuration word, devcfg1.
pic32mx330/350/370/430/450/470 ds60001185b-page 178 preliminary ? 2012-2013 microchip technology inc. 13.2 control register register 13-1: t1con: type a timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r-0 u-0 u-0 u-0 on (1) ? sidl twdis twip ? ? ? 7:0 r/w-0 u-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 u-0 tgate ? tckps<1:0> ? tsync tcs ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: timer on bit (1) 1 = timer is enabled 0 = timer is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation even in idle mode bit 12 twdis: asynchronous timer write disable bit 1 = writes to tmr1 are ignored until pending write operation completes 0 = back-to-back writes are enabled (legacy asynchronous timer functionality) bit 11 twip: asynchronous timer write in progress bit in asynchronous timer mode: 1 = asynchronous write to tmr1 register in progress 0 = asynchronous write to tmr1 register complete in synchronous timer mode: this bit is read as ? 0 ?. bit 10-8 unimplemented: read as ? 0 ? bit 7 tgate: timer gated time accumulation enable bit when tcs = 1 : this bit is ignored. when tcs = 0 : 1 = gated time accumulation is enabled 0 = gated time accumulation is disabled bit 6 unimplemented: read as ? 0 ? bit 5-4 tckps<1:0>: timer input clock pr escale select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 unimplemented: read as ? 0 ? note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 179 pic32mx330/350/370/430/450/470 bit 2 tsync: timer external clock input synchronization selection bit when tcs = 1 : 1 = external clock input is synchronized 0 = external clock input is not synchronized when tcs = 0 : this bit is ignored. bit 1 tcs: timer clock source select bit 1 = external clock from txcki pin 0 = internal peripheral clock bit 0 unimplemented: read as ? 0 ? register 13-1: t1con: type a time r control register (continued) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
pic32mx330/350/370/430/450/470 ds60001185b-page 180 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 181 pic32mx330/350/370/430/450/470 14.0 timer2/3, timer4/5 this family of pic32 devices features four synchronous 16-bit timers (default) that can operate as a free- running interval timer for various timing applications and counting external events. the following modes are supported: ? synchronous internal 16-bit timer ? synchronous internal 16-bit gated timer ? synchronous external 16-bit timer two 32-bit synchronous timers are available by combining timer2 with timer3 and timer4 with timer5. the 32-bit timers can operate in three modes: ? synchronous internal 32-bit timer ? synchronous internal 32-bit gated timer ? synchronous external 32-bit timer 14.1 additional supported features ? selectable clock prescaler ? timers operational during cpu idle ? time base for input capture and output compare modules (timer2 and timer3 only) ? adc event trigger (timer3 only) ? fast bit manipulation using clr, set and inv registers figure 14-1: timer2, 3, 4, 5 block diagram (16-bit) note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 14. ?timers? (ds60001105) of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. note: in this chapter, references to registers, txcon, tmrx and prx, use ?x? to repre - sent timer2 through 5 in 16-bit modes. in 32-bit modes, ?x? represents timer2 or 4; ?y? represents timer3 or 5. sync prx txif event flag equal comparator x 16 tmrx reset q qd tgate 1 0 gate txck sync on tgate tcs tckps prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 x 1 1 0 0 0 pbclk adc event trigger (1) note 1: the adc event trigger is available on timer3 only.
pic32mx330/350/370/430/450/470 ds60001185b-page 182 preliminary ? 2012-2013 microchip technology inc. figure 14-2: timer2/3, 4/5 block diagram (32-bit) (1) tmry tmrx tyif event flag equal 32-bit comparator pry prx reset ls half word ms half word note 1: in this diagram, the use of ?x? in register s, txcon, tmrx, prx and txck, refers to either timer2 or timer4; the use of ?y? in r egisters, tycon, tmry, pry, tyif, refers to either timer3 or timer5. 2: adc event trigger is available only on the timer2/3 pair. tgate 0 1 pbclk gate txck sync sync adc event trigger (2) on tgate tcs tckps prescaler 3 1, 2, 4, 8, 16, 32, 64, 256 1 0 0 0 q q d x 1
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 183 pic32mx330/350/370/430/450/470 14.2 control register register 14-1: txcon: type b timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on (1,3) ? sidl (4) ? ? ? ? ? 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 tgate (3) tckps<2:0> (3) t32 (2) ? tcs (3) ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: timer on bit (1,3) 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit (4) 1 = discontinue operation when device enters idle mode 0 = continue operation even in idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 tgate: timer gated time accumulation enable bit (3) when tcs = 1 : this bit is ignored and is read as ? 0 ?. when tcs = 0 : 1 = gated time accumu lation is enabled 0 = gated time accumu lation is disabled bit 6-4 tckps<2:0>: timer input clock prescale select bits (3) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: this bit is available only on even numbered timers (timer2 and timer4). 3: while operating in 32-bit mode, this bit has no ef fect for odd numbered timers (timer1, timer3, and tim - er5). all timer functions are set through the even numbered timers. 4: while operating in 32-bit mode, this bit must be clea red on odd numbered timers to enable the 32-bit timer in idle mode.
pic32mx330/350/370/430/450/470 ds60001185b-page 184 preliminary ? 2012-2013 microchip technology inc. bit 3 t32: 32-bit timer mode select bit (2) 1 = odd numbered and even numbered timers form a 32-bit timer 0 = odd numbered and even numbered timers form a separate 16-bit timer bit 2 unimplemented: read as ? 0 ? bit 1 tcs: timer clock source select bit (3) 1 = external clock from txck pin 0 = internal peripheral clock bit 0 unimplemented: read as ? 0 ? register 14-1: txcon: type b timer control register (continued) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: this bit is available only on even numbered timers (timer2 and timer4). 3: while operating in 32-bit mode, this bit has no ef fect for odd numbered timers (timer1, timer3, and tim- er5). all timer functions are set through the even numbered timers. 4: while operating in 32-bit mode, this bit must be cl eared on odd numbered timers to enable the 32-bit timer in idle mode.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 185 pic32mx330/350/370/430/450/470 15.0 input capture the input capture module is useful in applications requiring frequency (period) and pulse measurement. the input capture module capt ures the 16-bit or 32-bit value of the selected time base registers when an event occurs at the icx pin. the following events cause capture events: ? simple capture event modes - capture timer value on every falling edge of input at icx pin - capture timer value on every rising edge of input at icx pin ? capture timer value on every edge (rising and falling) ? capture timer value on every edge (rising and falling), specified edge first. ? prescaler capture event modes - capture timer value on every 4th rising edge of input at icx pin - capture timer value on every 16th rising edge of input at icx pin each input capture channel can select between one of two 16-bit timers (timer2 or timer3) for the time base, or two 16-bit timers (timer2 and timer3) together to form a 32-bit timer. the sele cted timer can use either an internal or external clock. other operational features include: ? device wake-up from capture pin during cpu sleep and idle modes ? interrupt on input capture event ? 4-word fifo buffer for capture values ? interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled ? input capture can also be used to provide additional sources of external interrupts figure 15-1: input capture block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 15. ?input capture? (ds60001122) of the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. note: an ?x? in a signal, register or bit name denotes the number of the capture channel. fifo control icxbuf tmr2 tmr3 capture event /n fifo ici<1:0> icm<2:0> icm<2:0> 101 100 011 010 001 001 111 to cpu set flag icxif (in ifsx register) rising edge mode prescaler mode (4th rising edge) falling edge mode edge detection prescaler mode (16th rising edge) sleep/idle wake-up mode c32/ictmr icx pin mode 110 specified/every edge mode fedge
pic32mx330/350/370/430/450/470 ds60001185b-page 186 preliminary ? 2012-2013 microchip technology inc. 15.1 control register register 15-1: ic x con: input capture ? x ? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 on (1) ? sidl ? ? ? fedge c32 7:0 r/w-0 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 ictmr ici<1:0> icov icbne icm<2:0> legend: r = readable bit w = writable bit u = unimplemented bit -n = bit value at por: (?0?, ?1?, x = unknown) p = programmable bit r = reserved bit bit 31-16 unimplemented: read as ? 0 ? bit 15 on: input capture module enable bit (1) 1 = module enabled 0 = disable and reset module, disable clocks, disable interrupt generation and allow sfr modifications bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle control bit 1 = halt in cpu idle mode 0 = continue to operate in cpu idle mode bit 12-10 unimplemented: read as ? 0 ? bit 9 fedge: first capture edge select bit (only used in mode 6, icm<2:0> = 110 ) 1 = capture rising edge first 0 = capture falling edge first bit 8 c32: 32-bit capture select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture bit 7 ictmr: timer select bit (does not affect timer selection when c32 (icxcon<8>) is ? 1 ?) 0 = timer3 is the counter source for capture 1 = timer2 is the counter source for capture bit 6-5 ici<1:0>: interrupt control bits 11 = interrupt on every fourth capture event 10 = interrupt on every third capture event 01 = interrupt on every second capture event 00 = interrupt on every capture event bit 4 icov: input capture overflow status flag bit (read-only) 1 = input capture overflow occurred 0 = no input capture overflow occurred bit 3 icbne: input capture buffer not empty status bit (read-only) 1 = input capture buffer is not empty; at least one more capture value can be read 0 = input capture buffer is empty note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 187 pic32mx330/350/370/430/450/470 bit 2-0 icm<2:0>: input capture mode select bits 111 = interrupt-only mode (only supported while in sleep mode or idle mode) 110 = simple capture event mode ? every edge, sp ecified edge first and every edge thereafter 101 = prescaled capture event mode ? every sixteenth rising edge 100 = prescaled capture event mode ? every fourth rising edge 011 = simple capture event mode ? every rising edge 010 = simple capture event mode ? every falling edge 001 = edge detect mode ? every edge (rising and falling) 000 = input capture module is disabled register 15-1: ic x con: input capture ? x ? control register (continued) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
pic32mx330/350/370/430/450/470 ds60001185b-page 188 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 189 pic32mx330/350/370/430/450/470 16.0 output compare the output compare module (ocmp) is used to gen - erate a single pulse or a trai n of pulses in response to selected time base events. for all modes of operation, the ocmp module compares the values stored in the ocxr and/or the ocxrs registers to the value in the selected timer. when a match occurs, the ocmp module generates an event based on the selected mode of operation. the following are some of the key features: ? multiple output compare modules in a device ? programmable interrupt generation on compare event ? single and dual compare modes ? single and continuous output pulse generation ? pulse-width modulation (pwm) mode ? hardware-based pwm fault detection and automatic output disable ? programmable selection of 16-bit or 32-bit time bases ? can operate from either of two available 16-bit time bases or a single 32-bit time base figure 16-1: output compare module block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 16. ?output compare? (ds6000 1111) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. ocxr (1) comparator output logic q s r ocm<2:0> output enable ocx (1) set flag bit ocxif (1) ocxrs (1) mode select 3 note 1: where ?x? is shown, reference is ma de to the registers associated with t he respective output compare channels, 1 through 5. 2: the ocfa pin controls the oc1-oc4 channels. the ocfb pin controls the oc5 channel. 0 1 octsel 0 1 16 16 ocfa or ocfb (2) timer2 timer2 timer3 logic output enable timer3 rollover rollover
pic32mx330/350/370/430/450/470 ds60001185b-page 190 preliminary ? 2012-2013 microchip technology inc. 16.1 control register register 16-1: ocxcon: output compare ?x? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on (1) ? sidl ? ? ? ? ? 7:0 u-0 u-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? oc32 ocflt (2) octsel ocm<2:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: output compare peripheral on bit (1) 1 = output compare peripheral is enabled 0 = output compare peripheral is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when cpu enters idle mode 0 = continue operation in idle mode bit 12-6 unimplemented: read as ? 0 ? bit 5 oc32: 32-bit compare mode bit 1 = ocxr<31:0> and/or ocxrs<31:0> are used fo r comparisions to the 32-bit timer source 0 = ocxr<15:0> and ocxrs<15:0> are used for comparisons to the 16-bit timer source bit 4 ocflt: pwm fault condition status bit (2) 1 = pwm fault condition has occurred (cleared in hw only) 0 = no pwm fault condition has occurred bit 3 octsel: output compare timer select bit 1 = timer3 is the clock source for this ocmp module 0 = timer2 is the clock s ource for this ocmp module bit 2-0 ocm<2:0>: output compare mode select bits 111 = pwm mode on ocx; fault pin enabled 110 = pwm mode on ocx; fault pin disabled 101 = initialize ocx pin low; generate continuous output pulses on ocx pin 100 = initialize ocx pin low; generate single output pulse on ocx pin 011 = compare event toggles ocx pin 010 = initialize ocx pin high; compare event forces ocx pin low 001 = initialize ocx pin low; compare event forces ocx pin high 000 = output compare peripheral is dis abled but continues to draw current note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: this bit is only used when ocm<2:0> = ? 111 ?. it is read as ? 0 ? in all other modes.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 191 pic32mx330/350/370/430/450/470 17.0 serial peripheral interface (spi) the spi module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. these peripheral devices may be serial eeprom s, shift registers, dis - play drivers, analog-to-digit al converters (adc), etc. the pic32 spi module is compatible with motorola ? spi and siop interfaces. some of the key features of the spi module are: ? master and slave modes support ? four different clock formats ? enhanced framed spi protocol support ? user-configurable 8-bit, 16-bit and 32-bit data width ? separate spi fifo buffers for receive and transmit - fifo buffers act as 4/8/16-level deep fifos based on 32/16/8-bit data width ? programmable interrupt event on every 8-bit, ? 16-bit and 32-bit data transfer ? operation during cpu sleep and idle mode ? audio codec support: -i 2 s protocol - left-justified - right-justified -pcm figure 17-1: spi module block diagram note 1: this data sheet summarizes the features of the pic32mx330/350/370/ 430/450/470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 23. ?serial peripheral interface (spi)? (ds60001106) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. internal data bus sdix sdox ssx /f sync sckx spixsr bit 0 shift control edge select msten baud rate slave select sync control clock control transmit receive and frame note: access spixtxb and spixrxb fifos via spixbuf register. fifos share address spixbuf spixbuf generator pbclk write read spixtxb fifo spixrxb fifo refclk mclksel
pic32mx330/350/370/430/450/470 ds60001185b-page 192 preliminary ? 2012-2013 microchip technology inc. 17.1 control registers register 17-1: spixcon: spi control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 frmen frmsync frmpol mssen frmsypw frmcnt<2:0> 23:16 r/w-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 mclksel (2) ? ? ? ? ? spife enhbuf (2) 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on (1) ? sidl dissdo mode32 mode16 smp cke (3) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ssen ckp (4) msten dissdi stxisel<1:0> srxisel<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 frmen: framed spi support bit 1 = framed spi support is enabled ( ssx pin used as fsync input/output) 0 = framed spi support is disabled bit 30 frmsync: frame sync pulse direction control on ssx pin bit (framed spi mode only) 1 = frame sync pulse input (slave mode) 0 = frame sync pulse output (master mode) bit 29 frmpol: frame sync polarity bit (framed spi mode only) 1 = frame pulse is active-high 0 = frame pulse is active-low bit 28 mssen: master mode slave select enable bit 1 = slave select spi support enabled. the ss pin is automatically driven during transmission in ? master mode. polarity is de termined by the frmpol bit. 0 = slave select spi support is disabled. bit 27 frmsypw: frame sync pulse width bit 1 = frame sync pulse is one character wide 0 = frame sync pulse is one clock wide bit 26-24 frmcnt<2:0>: frame sync pulse counter bits. controls the number of data characters transmitted per pulse. this bit is only valid in framed_sync mode. 111 = reserved; do not use 110 = reserved; do not use 101 = generate a frame sync pulse on every 32 data characters 100 = generate a frame sync pulse on every 16 data characters 011 = generate a frame sync pulse on every 8 data characters 010 = generate a frame sync pulse on every 4 data characters 001 = generate a frame sync pulse on every 2 data characters 000 = generate a frame sync pulse on every data character bit 23 mclksel: master clock enable bit (2) 1 = refclk is used by the baud rate generator 0 = pbclk is used by the baud rate generator note 1: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit. 2: this bit can only be wri tten when the on bit = 0 . 3: this bit is not used in the framed spi mode . the user should program this bit to ? 0 ? for the framed spi mode (frmen = 1 ). 4: when auden = 1 , the spi module functions as if the ckp bit is equal to ? 1 ?, regardless of the actual value of ckp.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 193 pic32mx330/350/370/430/450/470 bit 22-18 unimplemented: read as ? 0 ? bit 17 spife: frame sync pulse edge select bit (framed spi mode only) 1 = frame synchronization pulse coincides with the first bit clock 0 = frame synchronization pulse precedes the first bit clock bit 16 enhbuf: enhanced buffer enable bit (2) 1 = enhanced buffer mode is enabled 0 = enhanced buffer mode is disabled bit 15 on: spi peripheral on bit (1) 1 = spi peripheral is enabled 0 = spi peripheral is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when cpu enters in idle mode 0 = continue operation in idle mode bit 12 dissdo: disable sdox pin bit 1 = sdox pin is not used by the module. pin is controlled by associated port register 0 = sdox pin is controlled by the module bit 11-10 mode<32,16>: 32/16-bit communication select bits when auden = 1 : mode32 mode16 communication 11 24-bit data, 32-bit fifo, 32-bit channel/64-bit frame 10 32-bit data, 32-bit fifo, 32-bit channel/64-bit frame 01 16-bit data, 16-bit fifo, 32-bit channel/64-bit frame 00 16-bit data, 16-bit fifo, 16-bit channel/32-bit frame when auden = 0 : mode32 mode16 communication 1x 32-bit 01 16-bit 00 8-bit bit 9 smp: spi data input sample phase bit master mode (msten = 1 ): 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time slave mode (msten = 0 ): smp value is ignored when spi is used in slave mode. the module always uses smp = 0 . bit 8 cke: spi clock edge select bit (3) 1 = serial output data changes on transition from acti ve clock state to idle clock state (see ckp bit) 0 = serial output data changes on transition from idle clock state to active clock state (see ckp bit) bit 7 ssen: slave select enable (slave mode) bit 1 = ssx pin used for slave mode 0 = ssx pin not used for slave mode, pin controlled by port function. bit 6 ckp: clock polarity select bit (4) 1 = idle state for clock is a high level; active state is a low level 0 = idle state for clock is a low level; active state is a high level register 17-1: spixcon: spi co ntrol register (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit. 2: this bit can only be wri tten when the on bit = 0 . 3: this bit is not used in the framed spi mode . the user should program this bit to ? 0 ? for the framed spi mode (frmen = 1 ). 4: when auden = 1 , the spi module functions as if the ckp bit is equal to ? 1 ?, regardless of the actual value of ckp.
pic32mx330/350/370/430/450/470 ds60001185b-page 194 preliminary ? 2012-2013 microchip technology inc. bit 5 msten: master mode enable bit 1 = master mode 0 =slave mode bit 4 dissdi: disable sdi bit 1 = sdi pin is not used by the spi module (pin is controlled by port function) 0 = sdi pin is controlled by the spi module bit 3-2 stxisel<1:0>: spi transmit buffer empty interrupt mode bits 11 = interrupt is generated when the buffer is not full (has one or more empty elements) 10 = interrupt is generated when the buffer is empty by one-half or more 01 = interrupt is generated when th e buffer is completely empty 00 = interrupt is generated when the last transfer is shifted out of spisr and transmit operations are ? complete bit 1-0 srxisel<1:0>: spi receive buffer full interrupt mode bits 11 = interrupt is generated when the buffer is full 10 = interrupt is generated when the buf fer is full by one-half or more 01 = interrupt is generated when the buffer is not empty 00 = interrupt is generated when the last word in th e receive buffer is read (i.e., buffer is empty) register 17-1: spixcon: spi co ntrol register (continued) note 1: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit. 2: this bit can only be wri tten when the on bit = 0 . 3: this bit is not used in the framed spi mode . the user should program this bit to ? 0 ? for the framed spi mode (frmen = 1 ). 4: when auden = 1 , the spi module functions as if the ckp bit is equal to ? 1 ?, regardless of the actual value of ckp.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 195 pic32mx330/350/370/430/450/470 register 17-2: spixcon2: spi control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 spisgnext ? ? frmerren spiroven spituren ignrov igntur 7:0 r/w-0 u-0 u-0 u-0 r/w-0 u-0 r/w-0 r/w-0 auden (1) ? ? ? audmono (1,2) ? audmod<1:0> (1,2) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 spisgnext: sign extend read data from the rx fifo bit 1 = data from rx fifo is sign extended 0 = data from rx fifo is not sign extened bit 14-13 unimplemented: read as ? 0 ? bit 12 frmerren: enable interrupt events via frmerr bit 1 = frame error overflow generates error events 0 = frame error does not generate error events bit 11 spiroven: enable interrupt events via spirov bit 1 = receive overflow generates error events 0 = receive overflow does not generate error events bit 10 spituren: enable interrupt events via spitur bit 1 = transmit underrun generates error events 0 = transmit underrun does not generates error events bit 9 ignrov: ignore receive overflow bit (for audio data transmissions) 1 = a rov is not a critical error; during rov data in the fifo is not overwritten by receive data 0 = a rov is a critical error which stop spi operation bit 8 igntur: ignore transmit underrun bit (for audio data transmissions) 1 = a tur is not a critical error and zeros ar e transmitted until the spixtxb is not empty 0 = a tur is a critical error which stop spi operation bit 7 auden: enable audio codec support bit (1) 1 = audio protocol enabled 0 = audio protocol disabled bit 6-5 unimplemented: read as ? 0 ? bit 3 audmono: transmit audio data format bit (1,2) 1 = audio data is mono (each data word is transmitted on both left and right channels) 0 = audio data is stereo bit 2 unimplemented: read as ? 0 ? bit 1-0 audmod<1:0>: audio protocol mode bit (1,2) 11 = pcm/dsp mode 10 = right justified mode 01 = left justified mode 00 = i 2 s mode note 1: this bit can only be wri tten when the on bit = 0 . 2: this bit is only valid for auden = 1 .
pic32mx330/350/370/430/450/470 ds60001185b-page 196 preliminary ? 2012-2013 microchip technology inc. register 17-3: spixstat: spi status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 ? ? ? rxbufelm<4:0> 23:16 u-0 u-0 u-0 r-0 r-0 r-0 r-0 r-0 ? ? ? txbufelm<4:0> 15:8 u-0 u-0 u-0 r/c-0, hs r-0 u-0 u-0 r-0 ? ? ? frmerr spibusy ? ?spitur 7:0 r-0 r/w-0 r-0 u-0 r-1 u-0 r-0 r-0 srmt spirov spirbe ?spitbe ? spitbf spirbf legend: c = clearable bit hs = set in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-29 unimplemented: read as ? 0 ? bit 28-24 rxbufelm<4:0>: receive buffer element count bits (valid only when enhbuf = 1 ) bit 23-21 unimplemented: read as ? 0 ? bit 20-16 txbufelm<4:0>: transmit buffer element count bits (valid only when enhbuf = 1 ) bit 15-13 unimplemented: read as ? 0 ? bit 12 frmerr: spi frame error status bit 1 = frame error detected 0 = no frame error detected this bit is only valid when frmen = 1 . bit 11 spibusy: spi activity status bit 1 = spi peripheral is currently busy with some transactions 0 = spi peripheral is currently idle bit 10-9 unimplemented: read as ? 0 ? bit 8 spitur: transmit under run bit 1 = transmit buffer has encountered an underrun condition 0 = transmit buffer has no underrun condition this bit is only valid in framed sync mode; the underrun condition must be cleared by disabling/re-enabling the module. bit 7 srmt: shift register empty bit (valid only when enhbuf = 1 ) 1 = when spi module shift register is empty 0 = when spi module shift register is not empty bit 6 spirov: receive overflow flag bit 1 = a new data is completely received and discarded. the user software has not read the previous data in the spixbuf register. 0 = no overflow has occurred this bit is set in hardware; can only be cleared (= 0 ) in software. bit 5 spirbe: rx fifo empty bit (valid only when enhbuf = 1 ) 1 = rx fifo is empty (crptr = swptr) 0 = rx fifo is not empty (crptr ? ? swptr) bit 4 unimplemented: read as ? 0 ?
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 197 pic32mx330/350/370/430/450/470 bit 3 spitbe: spi transmit buffer empty status bit 1 = transmit buffer, spixtxb is empty 0 = transmit buffer, spixtxb is not empty automatically set in hardware when spi tr ansfers data from spixtxb to spixsr. automatically cleared in hardware when spixbuf is written to, loading spixtxb. bit 2 unimplemented: read as ? 0 ? bit 1 spitbf: spi transmit buffer full status bit 1 = transmit not yet started, spitxb is full 0 = transmit buffer is not full standard buffer mode: automatically set in hardware when the core writes to the spi buf location, loading spitxb. automatically cleared in hardware when the spi module transfers data from spitxb to spisr. enhanced buffer mode: set when cwptr + 1 = srptr; cleared otherwise bit 0 spirbf: spi receive buffer full status bit 1 = receive buffer, spixrxb is full 0 = receive buffer, spixrxb is not full standard buffer mode: automatically set in hardware when the spi module transfers data from spixsr to spixrxb. automatically cleared in hardware when spixbuf is read from, reading spixrxb. enhanced buffer mode: set when swptr + 1 = crptr; cleared otherwise register 17-3: spixstat: spi status register (continued)
pic32mx330/350/370/430/450/470 ds60001185b-page 198 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 199 pic32mx330/350/370/430/450/470 18.0 inter-integrated circuit? (i 2 c?) the i 2 c module provides complete hardware support for both slave and multi-master modes of the i 2 c serial communication standard. figure 18-1 illustrates the i 2 c module block diagram. each i 2 c module has a 2-pin interface: the sclx pin is clock and the sdax pin is data. each i 2 c module offers the fo llowing key features: ?i 2 c interface supporting both master and slave operation ?i 2 c slave mode supports 7-bit and 10-bit addressing ?i 2 c master mode supports 7-bit and 10-bit addressing ?i 2 c port allows bidirectional transfers between master and slaves ? serial clock synchronization for the i 2 c port can be used as a handshake mechanism to suspend and resume serial transfer (sclrel control) ?i 2 c supports multi-master operation; detects bus collision and arbitrates accordingly ? provides support for address bit masking note 1: this data sheet summarizes the features of the pic32mx330/350/370/ 430/450/470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 24. ?inter-integrated circuit? (i 2 c?)? (ds60001116) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information.
pic32mx330/350/370/430/450/470 ds60001185b-page 200 preliminary ? 2012-2013 microchip technology inc. figure 18-1: i 2 c? block diagram internal data bus sclx sdax shift match detect i2cxadd start and stop bit detect clock address match clock stretching i2cxtrn lsb shift clock brg down counter reload control pbclk start and stop bit generation acknowledge generation collision detect i2cxcon i2cxstat control logic read lsb write read i2cxbrg i2cxrsr write read write read write read write read write read i2cxmsk i2cxrcv
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 201 pic32mx330/350/370/430/450/470 18.1 control registers register 18-1: i2c x con: i 2 c? control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-1, hc r/w-0 r/w-0 r/w-0 r/w-0 on (1) ? sidl sclrel strict a10m disslw smen 7:0 r/w-0 r/w-0 r/w-0 r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc r/w-0, hc gcen stren ackdt acken rcen pen rsen sen legend: hc = cleared in hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: i 2 c enable bit (1) 1 = enables the i 2 c module and configures the sda and scl pins as serial port pins 0 = disables the i 2 c module; all i 2 c pins are controlled by port functions bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 sclrel: sclx release control bit (when operating as i 2 c slave) 1 = release sclx clock 0 = hold sclx clock low (clock stretch) if stren = 1 : bit is r/w (i.e., software can write ? 0 ? to initiate stretch and write ? 1 ? to release clock). hardware clear at beginning of slave transmission. hardwa re clear at end of slave reception. if stren = 0 : bit is r/s (i.e., software can only write ? 1 ? to release clock). hardware clear at beginning of slave ? transmission. bit 11 strict: strict i 2 c reserved address rule enable bit 1 = strict reserved addressing is enforced. device does not respond to reserved address space or generate addresses in reserved address space. 0 = strict i 2 c reserved address rule not enabled bit 10 a10m: 10-bit slave address bit 1 = i2cxadd is a 10-bit slave address 0 = i2cxadd is a 7-bit slave address bit 9 disslw: disable slew rate control bit 1 = slew rate control disabled 0 = slew rate control enabled bit 8 smen: smbus input levels bit 1 = enable i/o pin thresholds compliant with smbus specification 0 = disable smbus input thresholds note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
pic32mx330/350/370/430/450/470 ds60001185b-page 202 preliminary ? 2012-2013 microchip technology inc. bit 7 gcen: general call enable bit (when operating as i 2 c slave) 1 = enable interrupt when a general call address is received in the i2cxrsr ? (module is enabled for reception) 0 = general call address disabled bit 6 stren: sclx clock stretch enable bit (when operating as i 2 c slave) used in conjunction with sclrel bit. 1 = enable software or receive clock stretching 0 = disable software or receive clock stretching bit 5 ackdt: acknowledge data bit (when operating as i 2 c master, applicable during master receive) value that is transmitted when the soft ware initiates an acknowledge sequence. 1 = send nack during acknowledge 0 = send ack during acknowledge bit 4 acken: acknowledge sequence enable bit ? (when operating as i 2 c master, applicable during master receive) 1 = initiate acknowledge sequence on sdax and sclx pins and transmit ackdt data bit. ? hardware clear at end of ma ster acknowledge sequence. 0 = acknowledge sequence not in progress bit 3 rcen: receive enable bit (when operating as i 2 c master) 1 = enables receive mode for i 2 c. hardware clear at end of eighth bit of master receive data byte. 0 = receive sequence not in progress bit 2 pen: stop condition enable bit (when operating as i 2 c master) 1 = initiate stop condition on sdax and sclx pins. hardware clear at end of master stop sequence. 0 = stop condition not in progress bit 1 rsen: repeated start condition enable bit (when operating as i 2 c master) 1 = initiate repeated start condition on sdax and sclx pins. hardware clear at end of ? master repeated start sequence. 0 = repeated start condition not in progress bit 0 sen: start condition enable bit (when operating as i 2 c master) 1 = initiate start condition on sdax and sclx pins. hardware clear at end of master start sequence. 0 = start condition not in progress register 18-1: i2c x con: i 2 c? control register (continued) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 203 pic32mx330/350/370/430/450/470 register 18-2: i2c x stat: i 2 c? status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0, hsc r-0, hsc u-0 u-0 u-0 r/ c-0, hs r-0, hsc r-0, hsc ackstat trstat ? ? ? bcl gcstat add10 7:0 r/c-0, hs r/c-0, hs r-0, hsc r/c-0, hsc r/c-0, hsc r-0, hsc r-0, hsc r-0, hsc iwcol i2cov d_a p s r_w rbf tbf legend: hs = set in hardware hsc = hardware set/cleared r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared c = clearable bit bit 31-16 unimplemented: read as ? 0 ? bit 15 ackstat: acknowledge status bit ? (when operating as i 2 c? master, applicable to master transmit operation) 1 = nack received from slave 0 = ack received from slave hardware set or clear at end of slave acknowledge. bit 14 trstat: transmit status bit (when operating as i 2 c master, applicable to master transmit operation) 1 = master transmit is in progress (8 bits + ack) 0 = master transmit is not in progress hardware set at beginning of master transmission. hardware clear at end of slave acknowledge. bit 13-11 unimplemented: read as ? 0 ? bit 10 bcl: master bus collision detect bit 1 = a bus collision has been detec ted during a master operation 0 = no collision hardware set at detection of bus collision. bit 9 gcstat: general call status bit 1 = general call address was received 0 = general call address was not received hardware set when address matches general call address. hardware clear at stop detection. bit 8 add10: 10-bit address status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched hardware set at match of 2nd byte of matched 10 -bit address. hardware clear at stop detection. bit 7 iwcol: write collision detect bit 1 = an attempt to write the i2cx trn register failed because the i 2 c module is busy 0 = no collision hardware set at occurrence of write to i2cxtrn while busy (cleared by software). bit 6 i2cov: receive overflow flag bit 1 = a byte was received while the i2cxrcv re gister is still holding the previous byte 0 = no overflow hardware set at attempt to transfer i2cxrsr to i2cx rcv (cleared by software). bit 5 d_a: data/address bit (when operating as i 2 c slave) 1 = indicates that the last byte received was data 0 = indicates that the last byte received was device address hardware clear at device address match. hardware set by reception of slave byte.
pic32mx330/350/370/430/450/470 ds60001185b-page 204 preliminary ? 2012-2013 microchip technology inc. bit 4 p: stop bit 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 3 s: start bit 1 = indicates that a start (or repeated start) bit has been detected last 0 = start bit was not detected last hardware set or clear when start, repeated start or stop detected. bit 2 r_w: read/write information bit (when operating as i 2 c slave) 1 = read ? indicates data transfer is output from slave 0 = write ? indicates data transfer is input to slave hardware set or clear after reception of i 2 c device address byte. bit 1 rbf: receive buffer full status bit 1 = receive complete, i2cxrcv is full 0 = receive not complete, i2cxrcv is empty hardware set when i2cxrcv is written with received byte. hardware clear when software ? reads i2cxrcv. bit 0 tbf: transmit buffer full status bit 1 = transmit in progress, i2cxtrn is full 0 = transmit complete, i2cxtrn is empty hardware set when software writes i2cxtrn. hard ware clear at completion of data transmission. register 18-2: i2c x stat: i 2 c? status register (continued)
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 205 pic32mx330/350/370/430/450/470 19.0 universal asynchronous receiver transmitter (uart) the uart module is one of the serial i/o modules available in pic32mx330/35 0/370/430/450/470 family devices. the uart is a full-duplex, asynchronous communication channel t hat communicates with peripheral devices and personal computers through protocols, such as rs-232, rs-485, lin and irda ? . the module also supports the hardware flow control option, with uxcts and uxrts pins, and also includes an irda encoder and decoder. the primary features of the uart module are: ? full-duplex, 8-bit or 9-bit data transmission ? even, odd or no parity options (for 8-bit data) ? one or two stop bits ? hardware auto-baud feature ? hardware flow control option ? fully integrated baud ra te generator (brg) with 16-bit prescaler ? baud rates ranging from 76 bps to 20 mbps at 80 mhz ? 8-level deep first-in-first-out (fifo) transmit data buffer ? 8-level deep fifo receive data buffer ? parity, framing and buffer overrun error detection ? support for interrupt-only on address detect ? (9th bit = 1 ) ? separate transmit and receive interrupts ? loopback mode for diagnostic support ? lin protocol support ? irda encoder and decoder with 16x baud clock output for external irda encoder/decoder support figure 19-1 illustrates a simplified block diagram of the uart. figure 19-1: uart simplified block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 21. ?universal asynchronous receiver transmitter (uart)? (ds60001107) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. baud rate generator uxrx hardware flow control uartx receiver uartx transmitter uxtx uxcts uxrts / bclkx irda ? note: not all pins are available for all uart modules. refer to the device-specific pin di agram for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 206 preliminary ? 2012-2013 microchip technology inc. 19.1 control registers register 19-1: uxmode: uartx mode register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 on (1) ? sidl iren rtsmd ? uen<1:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wake lpback abaud rxinv brgh pdsel<1:0> stsel legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: uartx enable bit (1) 1 = uartx is enabled. uartx pins are controlled by uartx as defined by uen<1:0> and utxen ? control bits 0 = uartx is disabled. all uartx pins are controlled by corresponding bits in the portx, trisx and latx registers; uartx power consumption is minimal bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue operation when device enters idle mode 0 = continue operation in idle mode bit 12 iren: irda encoder and decoder enable bit 1 = irda is enabled 0 = irda is disabled bit 11 rtsmd: mode selection for uxrts pin bit 1 = uxrts pin is in simplex mode 0 = uxrts pin is in flow control mode bit 10 unimplemented: read as ? 0 ? bit 9-8 uen<1:0>: uartx enable bits 11 = uxtx, uxrx and uxbclk pins are enabled and used; uxcts pin is controlled by corresponding bits in the portx register 10 = uxtx, uxrx, uxcts and uxrts pins are enabled and used 01 = uxtx, uxrx and uxrts pins are enabled and used; uxcts pin is controlled by corresponding bits in the portx register 00 = uxtx and uxrx pins are enabled and used; uxcts and uxrts /uxbclk pins are controlled by corresponding bits in the portx register bit 7 wake: enable wake-up on start bit detect during sleep mode bit 1 = wake-up enabled 0 = wake-up disabled bit 6 lpback: uartx loopback mode select bit 1 = loopback mode is enabled 0 = loopback mode is disabled note 1: when using 1:1 pbclk divisor, the user software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 207 pic32mx330/350/370/430/450/470 bit 5 abaud: auto-baud enable bit 1 = enable baud rate measurement on the next characte r ? requires reception of sync character (0x55); cleared by hardware upon completion 0 = baud rate measurement disabled or completed bit 4 rxinv: receive polarity inversion bit 1 = uxrx idle state is ? 0 ? 0 = uxrx idle state is ? 1 ? bit 3 brgh: high baud rate enable bit 1 = high-speed mode ? 4x baud clock enabled 0 = standard speed mode ? 16x baud clock enabled bit 2-1 pdsel<1:0>: parity and data selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 stsel: stop selection bit 1 = 2 stop bits 0 = 1 stop bit register 19-1: uxmode: uartx mode register (continued) note 1: when using 1:1 pbclk divisor, the user software should not read/write the peripheral sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
pic32mx330/350/370/430/450/470 ds60001185b-page 208 preliminary ? 2012-2013 microchip technology inc. register 19-2: uxsta: uartx status and control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?adm_en 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-1 utxisel<1:0> utxinv urxen utxbrk utxen utxbf trmt 7:0 r/w-0 r/w-0 r/w-0 r-1 r-0 r-0 r/w-0 r-0 urxisel<1:0> adden ridle perr ferr oerr urxda legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-25 unimplemented: read as ? 0 ? bit 24 adm_en: automatic address detect mode enable bit 1 = automatic address detect mode is enabled 0 = automatic address detect mode is disabled bit 23-16 addr<7:0>: automatic address mask bits when the adm_en bit is ? 1 ?, this value defines the address character to use for automatic address detection. bit 15-14 utxisel<1:0>: tx interrupt mode selection bits 11 = reserved, do not use 10 = interrupt is generated and asserted while the transmit buffer is empty 01 = interrupt is generated and asserted w hen all characters have been transmitted 00 = interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 utxinv: transmit polarity inversion bit if irda mode is disabled (i.e., iren (uxmode<12>) is ? 0 ?): 1 = uxtx idle state is ? 0 ? 0 = uxtx idle state is ? 1 ? if irda mode is enabled (i.e., iren (uxmode<12>) is ? 1 ?): 1 = irda encoded uxtx idle state is ? 1 ? 0 = irda encoded uxtx idle state is ? 0 ? bit 12 urxen: receiver enable bit 1 = uartx receiver is enabled. uxrx pin is controlled by uartx (if on = 1 ) 0 = uartx receiver is disabled. uxrx pin is ignored by the uartx module. uxrx pin is controlled by port. bit 11 utxbrk: transmit break bit 1 = send break on next transmission. start bit followed by twelve ? 0 ? bits, followed by stop bit; cleared by hardware upon completion 0 = break transmission is disabled or completed bit 10 utxen: transmit enable bit 1 = uartx transmitter is enabled. uxtx pin is controlled by uartx (if on = 1 ) 0 = uartx transmitter is disabled. any pending transmi ssion is aborted and buffer is reset. uxtx pin is con- trolled by port. bit 9 utxbf: transmit buffer full status bit (read-only) 1 = transmit buffer is full 0 = transmit buffer is not full, at le ast one more character can be written bit 8 trmt: transmit shift register is empty bit (read-only) 1 = transmit shift register is empty and transmit buf fer is empty (the last transmission has completed) 0 = transmit shift register is not empty, a transmi ssion is in progress or queued in the transmit buffer
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 209 pic32mx330/350/370/430/450/470 bit 7-6 urxisel<1:0>: receive interrupt mode selection bit 11 = reserved; do not use 10 = interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters) 01 = interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters) 00 = interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character) bit 5 adden: address character detect bit (bit 8 of received data = 1 ) 1 = address detect mode is enabled. if 9-bit mode is not selected, this control bit has no effect 0 = address detect mode is disabled bit 4 ridle: receiver idle bit (read-only) 1 = receiver is idle 0 = data is being received bit 3 perr: parity error status bit (read-only) 1 = parity error has been detected for the current character 0 = parity error has not been detected bit 2 ferr: framing error status bit (read-only) 1 = framing error has been detected for the current character 0 = framing error has not been detected bit 1 oerr: receive buffer overrun error status bit. this bit is set in hardware and can only be cleared (= 0 ) in software. clearing a previously set oerr bit resets the receiver buffer and rsr to empty state. 1 = receive buffer has overflowed 0 = receive buffer has not overflowed bit 0 urxda: receive buffer data available bit (read-only) 1 = receive buffer has data, at least one more character can be read 0 = receive buffer is empty register 19-2: uxsta: uartx status and control register (continued)
pic32mx330/350/370/430/450/470 ds60001185b-page 210 preliminary ? 2012-2013 microchip technology inc. 19.2 timing diagrams figure 19-2 and figure 19-3 illustrate typical receive and transmit timing for the uart module. figure 19-2: uart reception figure 19-3: transmission (8-bit or 9-bit data) start 1 stop start 2 stop 4 start 5 stop 10 start 11 stop 13 read to uxrxreg uxrx ridle oerr uxrxif urxisel = 00 uxrxif urxisel = 01 uxrxif urxisel = 10 char 1 char 2-4 char 5-10 char 11-13 cleared by software cleared by software cleared by software start start bit 0 bit 1 stop write to tsr bclk/16 (shift clock) uxtx uxtxif uxtxif utxisel = 00 bit 1 uxtxreg utxisel = 01 uxtxif utxisel = 10 8 into txbuf pull from buffer
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 211 pic32mx330/350/370/430/450/470 20.0 parallel master port (pmp) the pmp is a parallel 8-bi t/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, lcds, external memory devices and microcontrollers. because the interface to parallel peripherals varies significantly, the pmp module is highly configurable. key features of the pmp module include: ? 8-bit,16-bit interface ? up to 16 programmable address lines ? up to two chip select lines ? programmable strobe options - individual read and write strobes, or - read/ write strobe with enable strobe ? address auto-increment/auto-decrement ? programmable address/data multiplexing ? programmable polarity on control signals ? parallel slave port support - legacy addressable - address support - 4-byte deep auto-incrementing buffer ? programmable wait states ? operate during cpu sleep and idle modes ? fast bit manipulation using clr, set and inv registers ? freeze option for in-circuit debugging figure 20-1: pmp module pinout and connections to external devices note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 13. ?parallel master port (pmp)? (ds60001128) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. note: on 64-pin devices, data pins pmd<15:8> are not available in 16-bit master modes. pma<0> pma<14> pmrd pmwr pmenb pmrd/pmwr pmcs1 pma<1> pma<13:2> pmall pmalh flash address bus data bus control lines lcd fifo microcontroller 8-bit/16-bit data (with or without multiplexed addressing) up to 16-bit address parallel buffer pmd<7:0> master port eeprom sram note: on 64-pin devices, data pins pmd<15:8> are not available in 16-bit master modes. pmd<15:8> (1) pma<15> pmcs2
pic32mx330/350/370/430/450/470 ds60001185b-page 212 preliminary ? 2012-2013 microchip technology inc. 20.1 control registers register 20-1: pmcon: parall el port control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on (1) ? sidl adrmux<1:0> pmpttl ptwren ptrden 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 csf<1:0> (2) alp (2) cs2p (2) cs1p (2) ? wrsp rdsp legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: parallel master port enable bit (1) 1 = pmp enabled 0 = pmp disabled, no off-chip access performed bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 adrmux<1:0>: address/data multiplexing selection bits 11 = lower 8 bits of address are multiplexed on pmd<15:0> pins; upper 8 bits are not used 10 = all 16 bits of address are multiplexed on pmd<15:0> pins 01 = lower 8 bits of address are multiplexed on pmd<7:0> pins, upper bits are on pma<10:8> and pma<14> 00 = address and data appear on separate pins bit 10 pmpttl: pmp module ttl input buffer select bit 1 = pmp module uses ttl input buffers 0 = pmp module uses schmitt trigger input buffer bit 9 ptwren: write enable strobe port enable bit 1 = pmwr/pmenb port enabled 0 = pmwr/pmenb port disabled bit 8 ptrden: read/write strobe port enable bit 1 = pmrd/pmwr port enabled 0 = pmrd/pmwr port disabled bit 7-6 csf<1:0>: chip select function bits (2) 11 = reserved 10 = pmcs1 function as chip select 01 = pmcs1 functions as address bit 14 00 = pmcs1 function as address bit 14 bit 5 alp: address latch polarity bit (2) 1 = active-high (pmall and pmalh) 0 = active-low ( pmall and pmalh ) note 1: when using 1:1 pbclk divisor, the user?s software s hould not read/write the peripheral?s sfrs in the sysclk cycle immediately followin g the instruction that clears the module?s on control bit. 2: these bits have no effect when their corresponding pins are used as address lines.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 213 pic32mx330/350/370/430/450/470 bit 4 cs2p: chip select 0 polarity bit (2) 1 = active-high (pmcs2) 0 = active-low ( pmcs2 ) bit 3 cs1p: chip select 0 polarity bit (2) 1 = active-high (pmcs1) 0 = active-low ( pmcs1 ) bit 2 unimplemented: read as ? 0 ? bit 1 wrsp: write strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00 , 01 , 10 ) : 1 = write strobe active-high (pmwr) 0 = write strobe active-low ( pmwr ) for master mode 1 (pmmode<9:8> = 11 ) : 1 = enable strobe active-high (pmenb) 0 = enable strobe active-low ( pmenb ) bit 0 rdsp: read strobe polarity bit for slave modes and master mode 2 (pmmode<9:8> = 00 , 01 , 10 ) : 1 = read strobe active-high (pmrd) 0 = read strobe active-low ( pmrd ) for master mode 1 (pmmode<9:8> = 11 ) : 1 = read/write strobe active-high (pmrd/ pmwr ) 0 = read/write strobe active-low ( pmrd /pmwr) register 20-1: pmcon: parallel po rt control register (continued) note 1: when using 1:1 pbclk divisor, the user?s software s hould not read/write the peripheral?s sfrs in the sysclk cycle immediately followin g the instruction that clears the module?s on control bit. 2: these bits have no effect when their corresponding pins are used as address lines.
pic32mx330/350/370/430/450/470 ds60001185b-page 214 preliminary ? 2012-2013 microchip technology inc. register 20-2: pmmode: para llel port mode register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 busy irqm<1:0> incm<1:0> ? mode<1:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 waitb<1:0> (1) waitm<3:0> (1) waite<1:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 busy: busy bit (master mode only) 1 = port is busy 0 = port is not busy bit 14-13 irqm<1:0>: interrupt request mode bits 11 = reserved, do not use 10 = interrupt generated when read buffer 3 is read or write buffer 3 is written (buffered psp mode) ? or on a read or write operation when pma<1:0> = 11 (addressable slave mode only) 01 = interrupt generated at the end of the read/write cycle 00 = no interrupt generated bit 12-11 incm<1:0>: increment mode bits 11 = slave mode read and write buffers auto-increment (pmmode<1:0> = 00 only) 10 = decrement addr<10:2> and addr <14> by 1 every read/write cycle (2) 01 = increment addr<10:2> and addr< 14> by 1 every read/write cycle (2) 00 = no increment or decrement of address bit 10 unimplemented: read as ? 0 ? bit 9-8 mode<1:0>: parallel port mode select bits 11 = master mode 1 (pmcs1, pmrd/pmwr, pmenb, pma , and pmd<15:0>) 10 = master mode 2 (pmcs1, pmrd, pmwr, pma, and pmd<15:0>) 01 = enhanced slave mode, control signals (pm rd, pmwr, pmcs1, pmd<15:0>, and pma<1:0>) 00 = legacy parallel slave port, control si gnals (pmrd, pmwr, pmcs1, and pmd<15:0>) bit 7-6 waitb<1:0>: data setup to read/write strobe wait states bits (1) 11 = data wait of 4 t pb ; multiplexed address phase of 4 t pb 10 = data wait of 3 t pb ; multiplexed address phase of 3 t pb 01 = data wait of 2 t pb ; multiplexed address phase of 2 t pb 00 = data wait of 1 t pb ; multiplexed address phase of 1 t pb (default) note 1: whenever waitm<3:0> = 0000 , waitb and waite bits are ignored and forced to 1 t pbclk cycle for a write operation; waitb = 1 t pbclk cycle, waite = 0 t pbclk cycles for a read operation. 2: address bit a14 is not subject to auto-increment /decrement if configured as chip select cs1.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 215 pic32mx330/350/370/430/450/470 bit 5-2 waitm<3:0>: data read/write strobe wait states bits (1) 1111 = wait of 16 t pb ? ? ? 0001 = wait of 2 t pb 0000 = wait of 1 t pb (default) bit 1-0 waite<1:0>: data hold after read/write strobe wait states bits (1) 11 = wait of 4 t pb 10 = wait of 3 t pb 01 = wait of 2 t pb 00 = wait of 1 t pb (default) for read operations: 11 = wait of 3 t pb 10 = wait of 2 t pb 01 = wait of 1 t pb 00 = wait of 0 t pb (default) register 20-2: pmmode: parallel port mode register (continued) note 1: whenever waitm<3:0> = 0000 , waitb and waite bits are ignored and forced to 1 t pbclk cycle for a write operation; waitb = 1 t pbclk cycle, waite = 0 t pbclk cycles for a read operation. 2: address bit a14 is not subject to auto-increment /decrement if configured as chip select cs1.
pic32mx330/350/370/430/450/470 ds60001185b-page 216 preliminary ? 2012-2013 microchip technology inc. register 20-3: pmaddr: parall el port address register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cs2 cs1 addr<13:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 addr<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as ? 0 ? bit 14 cs2: chip select 2 bit 1 = chip select 2 is active 0 = chip select 2 is inactive (pin functions as pma<14>) bit 14 cs1: chip select 1 bit 1 = chip select 1 is active 0 = chip select 1 is inactive (pin functions as pma<14>) bit 13-0 addr<13:0>: destination address bits
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 217 pic32mx330/350/370/430/450/470 register 20-4: pmaen: parallel port pin enable register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 r/w-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ?pten14 ? ? ?pten<10:8> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pten<7:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-15 unimplemented: read as ? 0 ? bit 15-14 pten14: pmcs1 strobe enable bits 1 = pma14 functions as either pma14 or pmcs1 (1) 0 = pma14 functions as port i/o bit 13-11 unimplemented: read as ? 0 ? bit 10-2 pten<10:2>: pmp address port enable bits 1 = pma<10:2> function as pmp address lines 0 = pma<10:2> function as port i/o bit 1-0 pten<1:0>: pmalh/pmall strobe enable bits 1 = pma1 and pma0 function as either pma<1:0> or pmalh and pmall (2) 0 = pma1 and pma0 pads functions as port i/o note 1: the use of this pin as pma14 or cs1 is selected by the csf<1:0> bits in the pmcon register. 2: the use of these pins as pma1/pma0 or pmalh/pm all depends on the address/data multiplex mode selected by bits adrmux<1:0> in the pmcon register.
pic32mx330/350/370/430/450/470 ds60001185b-page 218 preliminary ? 2012-2013 microchip technology inc. register 20-5: pmstat: parallel port status register (slave modes only) bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r-0 r/w-0, hsc u-0 u-0 r-0 r-0 r-0 r-0 ibf ibov ? ? ib3fib2fib1fib0f 7:0 r-1 r/w-0, hsc u-0 u-0 r-1 r-1 r-1 r-1 obe obuf ? ? ob3e ob2e ob1e ob0e legend: hsc = set by hardware; cleared by software r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 ibf: input buffer full status bit 1 = all writable input buffer registers are full 0 = some or all of the writable input buffer registers are empty bit 14 ibov: input buffer overflow status bit 1 = a write attempt to a full input byte buffer occurred (must be cleared in software) 0 = no overflow occurred bit 13-12 unimplemented: read as ? 0 ? bit 11-8 ibxf: input buffer ?x? status full bits 1 = input buffer contains data that has not been read (reading buffer will clear this bit) 0 = input buffer does not contain any unread data bit 7 obe: output buffer empty status bit 1 = all readable output buffer registers are empty 0 = some or all of the readable output buffer registers are full bit 6 obuf: output buffer underflow status bit 1 = a read occurred from an empty output byte buffer (must be cleared in software) 0 = no underflow occurred bit 5-4 unimplemented: read as ? 0 ? bit 3-0 obxe: output buffer ?x? status empty bits 1 = output buffer is empty (writing data to the buffer will clear this bit) 0 = output buffer contains data that has not been transmitted
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 219 pic32mx330/350/370/430/450/470 21.0 real-time clock and calendar (rtcc) the pic32 rtcc module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no cpu intervention. low-power optimization provides extended battery lifetime while keeping track of time. some of the key features of this module include: ? time: hours, minutes and seconds ? 24-hour format (military time) ? visibility of one-half second period ? provides calendar: weekday, date, month and year ? alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year ? alarm repeat with decrementing counter ? alarm with indefinite repeat: chime ? year range: 2000 to 2099 ? leap year correction ? bcd format for smalle r firmware overhead ? optimized for long-term battery operation ? fractional second synchronization ? user calibration of the clock crystal frequency with auto-adjust ? calibration range: ? 0.66 seconds error per month ? calibrates up to 260 ppm of crystal error ? requirements: external 32.768 khz clock crystal ? alarm pulse or seconds clock output on ? rtcc pin figure 21-1: rtcc block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 29. ?real- time clock and calendar (rtcc)? (ds60001125) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. rtcc prescalers rtcc timer comparator compare registers repeat counter alrmtime hr, min, sec alrmdate with masks rtcc interrupt logic alarm event 32.768 khz input from secondary 0.5s alarm pulse set rtcc flag rtcval alrmval rtcc rtcoe oscillator (s osc ) cal<9:0> month, day, wday rtctime hr, min, sec rtcdate year, month, day, wday seconds pulse rtsecsel 0 1
pic32mx330/350/370/430/450/470 ds60001185b-page 220 preliminary ? 2012-2013 microchip technology inc. 21.1 control registers register 21-1: rtccon: rtc control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? cal<9:8> 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cal<7:0> 15:8 r/w-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 on (1,2) ? sidl ? ? ? ? ? 7:0 r/w-0 r-0 u-0 u-0 r/w-0 r-0 r-0 r/w-0 rtsecsel (3) rtcclkon ? ? rtcwren (4) rtcsync halfsec (5) rtcoe legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-26 unimplemented: read as ? 0 ? bit 25-16 cal<9:0>: rtc drift calibration bits, which contain a signed 10-bit integer value 0111111111 = maximum positive adjustment, adds 511 rtc clock pulses every one minute ? ? ? 0000000001 = minimum positive adjustment, adds 1 rtc clock pulse every one minute 0000000000 = no adjustment 1111111111 = minimum negative adjustment, subtra cts 1 rtc clock pulse every one minute ? ? ? 1000000000 = minimum negative adjustment, subtra cts 512 clock pulses every one minute bit 15 on: rtcc on bit (1,2) 1 = rtcc module is enabled 0 = rtcc module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = disables the pbclk to the rtcc when cpu enters in idle mode 0 = continue normal operation in idle mode bit 12-8 unimplemented: read as ? 0 ? bit 7 rtsecsel: rtcc seconds clock output select bit (3) 1 = rtcc seconds clock is selected for the rtcc pin 0 = rtcc alarm pulse is selected for the rtcc pin bit 6 rtcclkon: rtcc clock enable status bit 1 = rtcc clock is actively running 0 = rtcc clock is not running bit 5-4 unimplemented: read as ? 0 ? note 1: the on bit is only writable when rtcwren = 1 . 2: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 3: requires rtcoe = 1 (rtccon<0>) for the output to be active. 4: the rtcwren bit can be set only when the write sequence is enabled. 5: this bit is read-only. it is cleared to ? 0 ? on a write to the seconds bit fields (rtctime<14:8>). note: this register is reset only on a power-on reset (por).
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 221 pic32mx330/350/370/430/450/470 bit 3 rtcwren: rtc value registers write enable bit (4) 1 = rtc value registers can be written to by the user 0 = rtc value registers are locked out from being written to by the user bit 2 rtcsync: rtcc value registers read synchronization bit 1 = rtc value registers can change while reading, due to a rollover ripple that results in an invalid data read if the register is read twice and results in th e same data, the data can be assumed to be valid 0 = rtc value registers can be read wi thout concern about a rollover ripple bit 1 halfsec: half-second status bit (5) 1 = second half period of a second 0 = first half period of a second bit 0 rtcoe: rtcc output enable bit 1 = rtcc clock output enabled ? clock presented onto an i/o 0 = rtcc clock output disabled register 21-1: rtccon: rtc co ntrol register (continued) note 1: the on bit is only writable when rtcwren = 1 . 2: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 3: requires rtcoe = 1 (rtccon<0>) for the output to be active. 4: the rtcwren bit can be set only when the write sequence is enabled. 5: this bit is read-only. it is cleared to ? 0 ? on a write to the seconds bit fields (rtctime<14:8>). note: this register is reset only on a power-on reset (por).
pic32mx330/350/370/430/450/470 ds60001185b-page 222 preliminary ? 2012-2013 microchip technology inc. register 21-2: rtcalrm: rtc alarm control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 alrmen (1,2) chime (2) piv (2) alrmsync (3) amask<3:0> (3) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 arpt<7:0> (3) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 alrmen: alarm enable bit (1,2) 1 = alarm is enabled 0 = alarm is disabled bit 14 chime: chime enable bit (2) 1 = chime is enabled ? arpt<7:0> is allowed to rollover from 0x00 to 0xff 0 = chime is disabled ? arpt<7:0> stops once it reaches 0x00 bit 13 piv: alarm pulse initial value bit (2) when alrmen = 0 , piv is writable and determines the initial value of the alarm pulse. when alrmen = 1 , piv is read-only and returns the state of the alarm pulse. bit 12 alrmsync: alarm sync bit (3) 1 = arpt<7:0> and alrmen may change as a result of a half second rollover during a read. ? the arpt must be read repeatedly until the same valu e is read twice. this mu st be done since multiple bits may be changing, which are then synchronized to the pb clock domain 0 = arpt<7:0> and alrmen can be read without concer ns of rollover because the prescaler is > 32 rtc clocks away from a half-second rollover bit 11-8 amask<3:0>: alarm mask configuration bits (3) 0000 = every half-second 0001 = every second 0010 = every 10 seconds 0011 = every minute 0100 = every 10 minutes 0101 = every hour 0110 = once a day 0111 = once a week 1000 = once a month 1001 = once a year (except when configured for february 29, once every four years) 1010 = reserved; do not use 1011 = reserved; do not use 11xx = reserved; do not use note 1: hardware clears the alrmen bit anytime th e alarm event occurs, when arpt<7:0> = 00 and chime = 0 . 2: this field should not be written when the rtcc on bit = ? 1 ? (rtccon<15>) and alrmsync = 1 . 3: this assumes a cpu read will execute in less than 32 pbclks. note: this register is reset only on a power-on reset (por).
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 223 pic32mx330/350/370/430/450/470 bit 7-0 arpt<7:0>: alarm repeat counter value bits (3) 11111111 = alarm will trigger 256 times ? ? ? 00000000 = alarm will trigger one time the counter decrements on any alarm event. the counter only rolls over from 0x00 to 0xff if chime = 1 . register 21-2: rtcalrm: rtc alarm control register (continued) note 1: hardware clears the alrmen bit anytime th e alarm event occurs, when arpt<7:0> = 00 and chime = 0 . 2: this field should not be written when the rtcc on bit = ? 1 ? (rtccon<15>) and alrmsync = 1 . 3: this assumes a cpu read will execute in less than 32 pbclks. note: this register is reset only on a power-on reset (por).
pic32mx330/350/370/430/450/470 ds60001185b-page 224 preliminary ? 2012-2013 microchip technology inc. register 21-3: rtctime: rtc time value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hr10<3:0> hr01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x min10<3:0> min01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sec10<3:0> sec01<3:0> 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 hr10<3:0>: binary-coded decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 hr01<3:0>: binary-coded decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 min10<3:0>: binary-coded decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 min01<3:0>: binary-coded decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 sec10<3:0>: binary-coded decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 sec01<3:0>: binary-coded decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 unimplemented: read as ? 0 ? note: this register is only writable when rtcwren = 1 (rtccon<3>).
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 225 pic32mx330/350/370/430/450/470 register 21-4: rtcdate: rtc date value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x year10<3:0> year01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x month10<3:0> month01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x day10<3:0> day01<3:0> 7:0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x ? ? ? ? wday01<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 year10<3:0>: binary-coded decimal value of years bits, 10 digits bit 27-24 year01<3:0>: binary-coded decimal value of years bits, 1 digit bit 23-20 month10<3:0>: binary-coded decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 month01<3:0>: binary-coded decimal value of months bits, 1 digit; contains a value from 0 to 9 bit 15-12 day10<3:0>: binary-coded decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 day01<3:0>: binary-coded decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 unimplemented: read as ? 0 ? bit 3-0 wday01<3:0>: binary-coded decimal value of weekdays bits,1 digit; contains a value from 0 to 6 note: this register is only writable when rtcwren = 1 (rtccon<3>).
pic32mx330/350/370/430/450/470 ds60001185b-page 226 preliminary ? 2012-2013 microchip technology inc. register 21-5: alrmtime: alarm time value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hr10<3:0> hr01<3:0> 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x min10<3:0> min01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x sec10<3:0> sec01<3:0> 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 hr10<3:0>: binary coded decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 hr01<3:0>: binary coded decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 min10<3:0>: binary coded decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 min01<3:0>: binary coded decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 sec10<3:0>: binary coded decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 sec01<3:0>: binary coded decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 unimplemented: read as ? 0 ?
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 227 pic32mx330/350/370/430/450/470 register 21-6: alrmdate: alarm date value register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x month10<3:0> month01<3:0> 15:8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x day10<1:0> day01<3:0> 7:0 u-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x ? ? ? ? wday01<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-24 unimplemented: read as ? 0 ? bit 23-20 month10<3:0>: binary coded decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 month01<3:0>: binary coded decimal value of months bits , 1 digit; contains a value from 0 to 9 bit 15-12 day10<3:0>: binary coded decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 day01<3:0>: binary coded decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 unimplemented: read as ? 0 ? bit 3-0 wday01<3:0>: binary coded decimal value of weekdays bits, 1 digit; contains a value from 0 to 6
pic32mx330/350/370/430/450/470 ds60001185b-page 228 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 229 pic32mx330/350/370/430/450/470 22.0 10-bit analog-to-digital converter (adc) the 10-bit analog-to-digital converter (adc) includes the following features: ? successive approximation register (sar) conversion ? up to 1 msps conversion speed ? up to 28 analog input pins ? external voltage reference input pins ? one unipolar, differential sample and hold amplifier (sha) ? automatic channel scan mode ? selectable conversion trigger source ? 16-word conversion result buffer ? selectable buffer fill modes ? eight conversion result format options ? operation during cpu sleep and idle modes a block diagram of the 10-bit adc is illustrated in figure 22-1 . the 10-bit adc has up to 28 analog input pins, designated an0-an27. in addition, there are two analog input pins for external voltage reference connections. these voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. figure 22-1: adc1 module block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 17. ?10-bit analog-to-digital converter (adc)? (ds60001104) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. sar adc s&h adc1buf0 adc1buf1 adc1buf2 adc1buff adc1bufe iv ref (3) ctmut (2) an1 v refl ch0sb<4:0> ch0na ch0nb + - ch0sa<4:0> channel scan cscna alternate v ref + (1) av dd av ss v ref - (1) note 1: v ref + and v ref - inputs can be multiplexed with other analog inputs. 2: connected to the ctmu module. see section 25.0 ?charge time measurement unit (ctmu)? for more information. 3: see section 24.0 ?comparator voltage reference (cv ref )? for more information. 4: this selection is only used with ct mu capacitive and time measurement. input selection v refh v refl vcfg<2:0> an27 an0 open (4) ctmui (3)
pic32mx330/350/370/430/450/470 ds60001185b-page 230 preliminary ? 2012-2013 microchip technology inc. figure 22-2: adc conversion clock period block diagram 1 0 div 2 t pb (2) adc conversion clock multiplier 2, 4,..., 512 adrc t ad 8 adcs<7:0> frc (1) note 1: see section 30.0 ?electrical characteristics? for the exact frc clock value. 2: refer to figure 8-1 in section 8.0 ?oscillator configuration? for more information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 231 pic32mx330/350/370/430/450/470 22.1 control registers register 22-1: ad1con1: adc control register 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 on (1) ? sidl ? ? form<2:0> 7:0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0, hsc r/c-0, hsc ssrc<2:0> clrasam ? asam samp (2) done (3) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: adc operating mode bit (1) 1 = adc module is operating 0 = adc module is not operating bit 14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12-11 unimplemented: read as ? 0 ? bit 10-8 form<2:0>: data output format bits 011 = signed fractional 16-bit (dout = 0000 0000 0000 0000 sddd dddd dd00 0000 ) 010 = fractional 16-bit (dout = 0000 0000 0000 0000 dddd dddd dd00 0000 ) 001 = signed integer 16-bit (dout = 0000 0000 0000 0000 ssss sssd dddd dddd ) 000 = integer 16-bit (dout = 0000 0000 0000 0000 0000 00dd dddd dddd ) 111 = signed fractional 32-bit (dout = sddd dddd dd00 0000 0000 0000 0000 ) 110 = fractional 32-bit (dout = dddd dddd dd00 0000 0000 0000 0000 0000 ) 101 = signed integer 32-bit (dout = ssss ssss ssss ssss ssss sssd dddd dddd ) 100 = integer 32-bit (dout = 0000 0000 0000 0000 0000 00dd dddd dddd ) bit 7-5 ssrc<2:0>: conversion trigger source select bits 111 = internal counter ends sampling and starts conversion (auto convert) 110 = reserved 101 = reserved 100 = reserved 011 = ctmu ends sampling and starts conversion 010 = timer 3 period match ends sampling and starts conversion 001 = active transition on int0 pin ends sampling and starts conversion 000 = clearing samp bit ends sampling and starts conversion note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: if asam = 0 , software can write a ? 1 ? to start sampling. this bit is automatically set by hardware if asam = 1 . if ssrc = 0 , software can write a ?0? to end sampling and start conversion. if ssrc ? ? ? 0 ?, this bit is automatically cleared by hardware to end sampling and start conversion. 3: this bit is automatically set by hardware when analog-to-digital conversion is complete. software can write a ? 0 ? to clear this bit (a write of ? 1 ? is not allowed). clearing this bit does not affect any operation already in progress. this bit is automatically clea red by hardware at the start of a new conversion.
pic32mx330/350/370/430/450/470 ds60001185b-page 232 preliminary ? 2012-2013 microchip technology inc. bit 4 clrasam: stop conversion sequence bit (when the first adc interrupt is generated) 1 = stop conversions when the first adc interrupt is generated. hardwa re clears the asam bit when the adc interrupt is generated. 0 = normal operation, buffer contents will be overwritten by the next conversion sequence bit 3 unimplemented: read as ? 0 ? bit 2 asam: adc sample auto-start bit 1 = sampling begins immediately after last conver sion completes; samp bi t is automatically set. 0 = sampling begins when samp bit is set bit 1 samp: adc sample enable bit (2) 1 = the adc sample and hold amplifier is sampling 0 = the adc sample/hold amplifier is holding when asam = 0 , writing ? 1 ? to this bit starts sampling. when ssrc = 000 , writing ? 0 ? to this bit will end sampling and start conversion. bit 0 done: analog-to-digital conversion status bit (3) 1 = analog-to-digital conversion is done 0 = analog-to-digital conversion is not done or has not started clearing this bit will not affect any operation in progress. register 22-1: ad1con1: adc cont rol register 1 (continued) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: if asam = 0 , software can write a ? 1 ? to start sampling. this bit is automatically set by hardware if asam = 1 . if ssrc = 0 , software can write a ?0? to end sampling and start conversion. if ssrc ? ? ? 0 ?, this bit is automatically cleared by hardware to end sampling and start conversion. 3: this bit is automatically set by hardware when analog-to-digital conversion is complete. software can write a ? 0 ? to clear this bit (a write of ? 1 ? is not allowed). clearing this bit does not affect any operation already in progress. this bit is automatically clear ed by hardware at the start of a new conversion.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 233 pic32mx330/350/370/430/450/470 register 22-2: ad1con2: adc control register 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 u-0 u-0 vcfg<2:0> offcal ?cscna ? ? 7:0 r-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 bufs ? smpi<3:0> bufm alts legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-13 vcfg<2:0>: voltage reference configuration bits v refh v refl 000 av dd avss 001 external v ref + pin av ss 010 av dd external v ref - pin 011 external v ref + pin external v ref - pin 1xx av dd av ss bit 12 offcal: input offset calibration mode select bit 1 = enable offset calibration mode ? positive and negative inputs of the sample and hold amplifier are connected to v refl 0 = disable offset calibration mode ? the inputs to the sample and hold amplifier are controlled by ad1chs or ad1cssl bit 11 unimplemented: read as ? 0 ? bit 10 cscna: input scan select bit 1 = scan inputs 0 = do not scan inputs bit 9-8 unimplemented: read as ? 0 ? bit 7 bufs: buffer fill status bit only valid when bufm = 1 . 1 = adc is currently filling buffer 0x8-0xf, user should access data in 0x0-0x7 0 = adc is currently filling buffer 0x0-0x7, user should access data in 0x8-0xf bit 6 unimplemented: read as ? 0 ? bit 5-2 smpi<3:0>: sample/convert sequences per interrupt selection bits 1111 = interrupts at the completion of conversion for each 16 th sample/convert sequence 1110 = interrupts at the completion of conversion for each 15 th sample/convert sequence ? ? ? 0001 = interrupts at the completion of conversion for each 2 nd sample/convert sequence 0000 = interrupts at the completion of conv ersion for each sample/convert sequence bit 1 bufm: adc result buffer mode select bit 1 = buffer configured as two 8-word buffers, adc1buf7-adc1buf0, adc1buff-adcbuf8 0 = buffer configured as one 16-word buffer adc1buff-adc1buf0 bit 0 alts: alternate input sample mode select bit 1 = uses sample a input multiplexer settings for first sample, then alternates between sample b and ? sample a input multiplexer settings for all subsequent samples 0 = always use sample a input multiplexer settings
pic32mx330/350/370/430/450/470 ds60001185b-page 234 preliminary ? 2012-2013 microchip technology inc. register 22-3: ad1con3: adc control register 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adrc ? ? samc<4:0> (1) 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w r/w-0 adcs<7:0> (2) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 adrc: adc conversion clock source bit 1 = clock derived from frc 0 = clock derived from peripheral bus clock (pbclk) bit 14-13 unimplemented: read as ? 0 ? bit 12-8 samc<4:0>: auto-sample time bits (1) 11111 =31 t ad ? ? ? 00001 = 1 t ad 00000 = 0 t ad (not allowed) bit 7-0 adcs<7:0>: adc conversion clock select bits (2) 11111111 =t pb ? 2 ? (adcs<7:0> + 1) = 512 ? t pb = t ad ? ? ? 00000001 =t pb ? 2 ? (adcs<7:0> + 1) = 4 ? t pb = t ad 00000000 =t pb ? 2 ? (adcs<7:0> + 1) = 2 ? t pb = t ad note 1: this bit is only used if the ss rc<2:0> bits (ad1con1<7:5>) = 111 . 2: this bit is not used if the adrc bit (ad1con3<15>) = 1 .
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 235 pic32mx330/350/370/430/450/470 register 22-4: ad1chs: adc input select register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0nb ? ? ch0sb<4:0> 23:16 r/w-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ch0na ? ? ch0sa<4:0> 15:8 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 ch0nb: negative input select bit for sample b 1 = channel 0 negative input is an1 0 = channel 0 negative input is v refl bit 30-29 unimplemented: read as ? 0 ? bit 28-24 ch0sb<4:0>: positive input select bits for sample b 11110 = channel 0 positive input is open (1) 11101 = channel 0 positive input is ct mu temperature sensor (ctmut) (2) 11100 = channel 0 positive input is iv ref (3) 11011 = channel 0 positive input is an27 ? ? ? 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 bit 23 ch0na: negative input select bit fo r sample a multiplexer setting (3) 1 = channel 0 negative input is an1 0 = channel 0 negative input is v refl bit 22-21 unimplemented: read as ? 0 ? bit 20-16 ch0sa<4:0>: positive input select bits fo r sample a multiplexer setting 11110 = channel 0 positive input is open (1) 11101 = channel 0 positive input is ct mu temperature sensor (ctmut) (2) 11100 = channel 0 positive input is iv ref (3) 11011 = channel 0 positive input is an27 ? ? ? 00001 = channel 0 positive input is an1 00000 = channel 0 positive input is an0 bit 15-0 unimplemented: read as ? 0 ? note 1: this selection is only used with ct mu capacitive and time measurement. 2: see section 25.0 ?charge time measurement unit (ctmu)? for more information. 3: see section 24.0 ?comparator voltage reference (cv ref )? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 236 preliminary ? 2012-2013 microchip technology inc. register 22-5: ad1cssl: adc input scan select register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cssl30 cssl29 cssl28 cssl27 cssl26 cssl25 cssl24 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl23 cssl21 cssl21 cssl20 cssl19 cssl18 cssl17 cssl16 15:8 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl15 cssl14 cssl13 cssl12 cssl11 cssl10 cssl9 cssl8 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cssl7 cssl6 cssl5 cssl4 cssl3 cssl2 cssl1 cssl0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15-0 cssl<30:0>: adc input pin scan selection bits (1,2) 1 = select anx for input scan 0 = skip anx for input scan note 1: cssl = anx, where x = 0-27; cssl30 selects vss for scan; cssl29 select s ctmu input for scan; cssl28 selects iv ref for scan. 2: on devices with less than 28 analog inputs, all csslx bits can be selected; however, inputs selected for scan without a corresponding input on the device will convert to v refl .
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 237 pic32mx330/350/370/430/450/470 23.0 comparator the analog comparator module contains two compar - ators that can be configured in a variety of ways. following are some of the key features of this module: ? selectable inputs available include: - analog inputs multiplexed with i/o pins - on-chip internal absolute voltage reference (iv ref ) - comparator voltage reference (cv ref ) ? outputs can be inverted ? selectable interrupt generation a block diagram of the comp arator module is provided in figure 23-1 . figure 23-1: comparator block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 19. ?comparator? (ds60001110) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. cv ref (1) iv ref (1.2v) c2ind c2ina c2out cmp2 coe cref cch<1:0> cpol c2inc c2inb c1ind c1ina c1out cmp1 coe cref cch<1:0> cpol c1inc c1inb cmstat cm1con cmstat cm2con to ctmu module (pulse generator) note 1: internally connected. see section 24.0 ?comparator voltage reference (cv ref )? for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 238 preliminary ? 2012-2013 microchip technology inc. 23.1 control registers register 23-1: cmxcon: co mparator control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 r-0 on (1) coe cpol (2) ? ? ? ? cout 7:0 r/w-1 r/w-1 u-0 r/w-0 u-0 u-0 r/w-1 r/w-1 evpol<1:0> ? cref ? ? cch<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: comparator on bit (1) 1 = module is enabled. setting this bit does not affect the other bits in this register 0 = module is disabled and does not consume current. clearing this bit does not affect the other bits in this register bit 14 coe: comparator output enable bit 1 = comparator output is driven on the output cxout pin 0 = comparator output is not driven on the output cxout pin bit 13 cpol: comparator output inversion bit (2) 1 = output is inverted 0 = output is not inverted bit 12-9 unimplemented: read as ? 0 ? bit 8 cout: comparator output bit 1 = output of the comparator is a ? 1 ? 0 = output of the comparator is a ? 0 ? bit 7-6 evpol<1:0>: interrupt event polarity select bits 11 = comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = comparator interrupt is generated on a high-to-low transition of the comparator output 01 = comparator interrupt is generated on a low-to-high transition of the comparator output 00 = comparator interrupt generation is disabled bit 5 unimplemented: read as ? 0 ? bit 4 cref: comparator positive input configure bit 1 = comparator non-inverting input is connected to the internal cv ref 0 = comparator non-inverting input is connected to the c x ina pin bit 3-2 unimplemented: read as ? 0 ? bit 1-0 cch<1:0>: comparator negative input select bits for comparator 11 = comparator inverting input is connected to the iv ref 10 = comparator inverting input is connected to the cxind pin 01 = comparator inverting input is connected to the cxinc pin 00 = comparator inverting input is connected to the cxinb pin note 1: when using the 1:1 pbclk divisor, the user?s software should not read/write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit. 2: setting this bit will invert the signal to the comparator interrupt generator as well. this will result in an interrupt being generated on the opposite edge from the one se lected by evpol<1:0>.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 239 pic32mx330/350/370/430/450/470 register 23-2: cmstat: comparator status register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 r/w-0 u-0 u-0 u-0 u-0 u-0 ? ?sidl ? ? ? ? ? 7:0 u-0 u-0 u-0 u-0 u-0 u-0 r-0 r-0 ? ? ? ? ? ?c2outc1out legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-14 unimplemented: read as ? 0 ? bit 13 sidl: stop in idle control bit 1 = all comparator modules are disabled in idle mode 0 = all comparator modules continue to operate in the idle mode bit 12-2 unimplemented: read as ? 0 ? bit 1 c2out: comparator output bit 1 = output of comparator 2 is a ? 1 ? 0 = output of comparator 2 is a ? 0 ? bit 0 c1out: comparator output bit 1 = output of comparator 1 is a ? 1 ? 0 = output of comparator 1 is a ? 0 ?
pic32mx330/350/370/430/450/470 ds60001185b-page 240 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 241 pic32mx330/350/370/430/450/470 24.0 comparator voltage reference (cv ref ) the cv ref module is a 16-tap, resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it al so may be used independently of them. a block diagram of the module is illustrated in figure 24-1 . the resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. the module?s supply refer - ence can be provided from either device v dd /v ss or an external voltage reference. the cv ref output is avail - able for the comparators and typically available for pin output. the cv ref module has the following features: ? high and low range selection ? sixteen output levels available for each range ? internally connected to comparators to conserve device pins ? output can be connected to a pin figure 24-1: comparator voltage reference block diagram note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the inform ation in this data sheet, refer to section 20. ?comparator voltage reference (cv ref )? (ds60001109) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32) . 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. 16-to-1 mux cvr<3:0> 8r r cvren cvrss = 0 av dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv refout av ss cvrcon cv ref cv rsrc
pic32mx330/350/370/430/450/470 ds60001185b-page 242 preliminary ? 2012-2013 microchip technology inc. 24.1 control register register 24-1: cvrcon: comparator voltage reference control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 on (1) ? ? ? ? ? ? ? 7:0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cvroe cvrr cvrss cvr<3:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: comparator voltage reference on bit (1) 1 = module is enabled ? setting this bit does not affect other bits in the register. 0 = module is disabled and does not consume current. ? clearing this bit does not affect the other bits in the register. bit 14-7 unimplemented: read as ? 0 ? bit 6 cvroe: cv refout enable bit 1 = v oltage level is output on cv refout pin 0 = v oltage level is disconnected from cv refout pin bit 5 cvrr: cv ref range selection bit 1 = 0 to 0.67 cv rsrc , with cv rsrc /24 step size 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size bit 4 cvrss: cv ref source selection bit 1 = comparator voltage reference source, cv rsrc = (v ref +) ? (v ref -) 0 = comparator voltage reference source, cv rsrc = av dd ? av ss bit 3-0 cvr<3:0>: cv ref value selection 0 ? cvr<3:0> ? 15 bits when cvrr = 1 : cv ref = (cvr<3:0>/24) ? (cv rsrc ) when cvrr = 0 : cv ref = 1/4 ? (cv rsrc ) + (cvr<3:0>/32) ? (cv rsrc ) note 1: when using 1:1 pbclk divisor, the user?s software should not read/write the per ipheral?s sfrs in the sysclk cycle immediately follo wing the instruction that cl ears the module?s on bit.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 243 pic32mx330/350/370/430/450/470 25.0 charge time measurement unit (ctmu) the charge time measurement unit (ctmu) is a flex - ible analog module that has a configurable current source with a digital configur ation circuit built around it. the ctmu can be used for differential time measure - ment between pulse sources and can be used for gen - erating an asynchronous pulse. by working with other on-chip analog modules, the ctmu can be used for high resolution time measurement, measure capaci - tance, measure relative changes in capacitance or generate output pulses with a specific time delay. the ctmu is ideal for interfacing with capacitive-based sensors. the ctmu module includes the following key features: ? up to 13 channels available for capacitive or time measurement input ? on-chip precision current source ? 16-edge input trigger sources ? selection of edge or level-sensitive inputs ? polarity control for each edge source ? control of edge sequence ? control of response to edges ? high precision time measurement ? time delay of external or internal signal asynchro - nous to system clock ? integrated temperature sensing diode ? control of current source during auto-sampling ? four current source ranges ? time measurement resolution of one nanosecond a block diagram of the ctmu is shown in figure 25-1 . figure 25-1: ctmu block diagram note 1: this data sheet summarizes the fea - tures of the pic32mx330/350/370/430/ 450/470 family of devices. it is not intended to be a comprehensive refer - ence source. to complement the infor - mation in this data sheet, refer to section 37. ?charge time measure - ment unit (ctmu)? (ds60001167) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information. cted1 cted13 current source edge control logic ctmucon1 or ctmucon2 pulse generator ctmui comparator 2 timer1 oc1 current control itrim<5:0> irng<1:0> ctmuicon ctmu control logic edg1stat edg2stat adc ctpls ic1-ic3 cmp1-cmp2 c2inb cdelay ctmut temperature sensor current control selection tgen edg1stat, edg2stat ctmut 0 edg1stat = edg2stat ctmui 0 edg1stat ? edg2stat ctmup 1 edg1stat ? edg2stat no connect 1 edg1stat = edg2stat trigger tgen ctmup external capacitor for pulse generation (to adc s&h capacitor) (to adc) pbclk ? ? ?
pic32mx330/350/370/430/450/470 ds60001185b-page 244 preliminary ? 2012-2013 microchip technology inc. 25.1 control register register 25-1: ctmucon: ctmu control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 edg1mod edg1pol edg1sel<3:0> edg2stat edg1stat 23:16 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 edg2mod edg2pol edg2sel<3:0> ? ? 15:8 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 on ? ctmusidl tgen (1) edgen edgseqen idissen (2) cttrig 7:0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 itrim<5:0> irng<1:0> legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 edg1mod: edge1 edge sampling select bit 1 = input is edge-sensitive 0 = input is level-sensitive bit 30 edg1pol: edge 1 polarity select bit 1 = edge1 programmed for a positive edge response 0 = edge1 programmed for a negative edge response bit 29-26 edg1sel<3:0>: edge 1 source select bits 1111 = c3out pin is selected 1110 = c2out pin is selected 1101 = c1out pin is selected 1100 = ic3 capture event is selected 1011 = ic2 capture event is selected 1010 = ic1 capture event is selected 1001 = cted8 pin is selected 1000 = cted7 pin is selected 0111 = cted6 pin is selected 0110 = cted5 pin is selected 0101 = cted4 pin is selected 0100 = cted3 pin is selected 0011 = cted1 pin is selected 0010 = cted2 pin is selected 0001 = oc1 compare event is selected 0000 = timer1 event is selected bit 25 edg2stat: edge2 status bit indicates the status of edge2 and can be written to control edge source 1 = edge2 has occurred 0 = edge2 has not occurred note 1: when this bit is set for pulse delay generation, the edg2sel<2:0> bits must be set to ? 1110 ? to select c2out. 2: the adc module sample and hold capacitor is not automatically discharged between sample/conversion cycles. software using the adc as pa rt of a capacitive measurement, must discharge the adc capacitor before conducting the measurement. the idissen bit, when set to ? 1 ?, performs this function. the adc module must be sampling while the idissen bit is active to connect the discharge sink to the capacitor array. 3: refer to the ctmu current source specifications ( ta b l e 30-41 ) in section 30.0 ?electrical characteristics? for current values. 4: this bit setting is not available for the ctmu temperature diode.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 245 pic32mx330/350/370/430/450/470 bit 24 edg1stat: edge1 status bit indicates the status of edge1 and can be written to control edge source 1 = edge1 has occurred 0 = edge1 has not occurred bit 23 edg2mod: edge2 edge sampling select bit 1 = input is edge-sensitive 0 = input is level-sensitive bit 22 edg2pol: edge 2 polarity select bit 1 = edge2 programmed for a positive edge response 0 = edge2 programmed for a negative edge response bit 21-18 edg2sel<3:0>: edge 2 source select bits 1111 = c3out pin is selected 1110 = c2out pin is selected 1101 = c1out pin is selected 1100 = pbclk clock is selected 1011 = ic3 capture event is selected 1010 = ic2 capture event is selected 1001 = ic1 capture event is selected 1000 = cted13 pin is selected 0111 = cted12 pin is selected 0110 = cted11 pin is selected 0101 = cted10 pin is selected 0100 = cted9 pin is selected 0011 = cted1 pin is selected 0010 = cted2 pin is selected 0001 = oc1 compare event is selected 0000 = timer1 event is selected bit 17-16 unimplemented: read as ? 0 ? bit 15 on: on enable bit 1 = module is enabled 0 = module is disabled bit 14 unimplemented: read as ? 0 ? bit 13 ctmusidl: stop in idle mode bit 1 = discontinue module operation when device enters idle mode 0 = continue module operation in idle mode bit 12 tgen: time generation enable bit (1) 1 = enables edge delay generation 0 = disables edge delay generation bit 11 edgen: edge enable bit 1 = edges are not blocked 0 = edges are blocked register 25-1: ctmucon: ctmu control register (continued) note 1: when this bit is set for pulse delay generatio n, the edg2sel<2:0> bits must be set to ? 1110 ? to select c2out. 2: the adc module sample and hold capacitor is not automatically discharged between sample/conversion cycles. software using the adc as pa rt of a capacitive measurement, must discharge the adc capacitor before conducting the measurement . the idissen bit, when set to ? 1 ?, performs this function. the adc module must be sampling while the idissen bit is active to connect the discharge sink to the capacitor array. 3: refer to the ctmu current source specifications ( table 30-41 ) in section 30.0 ?electrical characteristics? for current values. 4: this bit setting is not available for the ctmu temperature diode.
pic32mx330/350/370/430/450/470 ds60001185b-page 246 preliminary ? 2012-2013 microchip technology inc. bit 10 edgseqen: edge sequence enable bit 1 = edge1 must occur before edge2 can occur 0 = no edge sequence is needed bit 9 idissen: analog current source control bit (2) 1 = analog current source output is grounded 0 = analog current source output is not grounded bit 8 cttrig: trigger control bit 1 = trigger output is enabled 0 = trigger output is disabled bit 7-2 itrim<5:0>: current source trim bits 011111 = maximum positive change from nominal current 011110 ? ? ? 000001 = minimum positive change from nominal current 000000 = nominal current output specified by irng<1:0> 111111 = minimum negative change from nominal current ? ? ? 100010 100001 = maximum negative change from nominal current bit 1-0 irng<1:0>: current range select bits (3) 11 = 100 times base current 10 = 10 times base current 01 = base current level 00 = 1000 times base current (4) register 25-1: ctmucon: ctmu control register (continued) note 1: when this bit is set for pulse delay generation, the edg2sel<2:0> bits must be set to ? 1110 ? to select c2out. 2: the adc module sample and hold capacitor is not automatically discharged between sample/conversion cycles. software using the adc as pa rt of a capacitive measurement, must discharge the adc capacitor before conducting the measurement. the idissen bit, when set to ? 1 ?, performs this function. the adc module must be sampling while the idissen bit is active to connect the discharge sink to the capacitor array. 3: refer to the ctmu current source specifications ( table 30-41 ) in section 30.0 ?electrical characteristics? for current values. 4: this bit setting is not available for the ctmu temperature diode.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 247 pic32mx330/350/370/430/450/470 26.0 power-saving features this section describes power-saving features for the pic32mx330/350/370/430/450/470. the pic32 devices offer a total of nine methods and modes, organized into two categories, that allow the user to balance power consumption with device performance. in all of the methods and modes described in this section, power- saving is controlled by software. 26.1 power saving with cpu running when the cpu is running, power consumption can be controlled by reducing the cpu clock frequency, lowering the pbclk and by individually disabling modules. these methods are grouped into the following categories: ? frc run mode: the cpu is clocked from the frc clock source with or without postscalers. ? lprc run mode: the cpu is clocked from the lprc clock source. ?s osc run mode: the cpu is clocked from the s osc clock source. in addition, the peripheral bus scaling mode is available where peripherals are clocked at the programmable fraction of the cpu clock (sysclk). 26.2 cpu halted methods the device supports two power-saving modes, sleep and idle, both of which halt the clock to the cpu. these modes operate with all clock sources, as listed below: ?p osc idle mode: the system clock is derived from the p osc . the system clock source continues to operate. peripherals continue to operate, but can optionally be individually disabled. ? frc idle mode: the system clock is derived from the frc with or without postscalers. peripherals continue to operate, but can optionally be individually disabled. ?s osc idle mode: the system clock is derived from the s osc . peripherals continue to operate, but can optionally be individually disabled. ? lprc idle mode: the system clock is derived from the lprc. peripherals cont inue to operate, but can optionally be individua lly disabled. this is the lowest power mode for the device with a clock running. ? sleep mode: the cpu, the system clock source and any peripherals that operate from the system clock source are halted. some peripherals can operate in sleep using specific clock sources. this is the lowest power mode for the device. 26.3 power-saving operation peripherals and the cpu can be halted or disabled to further reduce power consumption. 26.3.1 sleep mode sleep mode has the lowest power consumption of the device power-saving operating modes. the cpu and most peripherals are halted. select peripherals can continue to operate in sleep mode and can be used to wake the device from sleep. see the individual peripheral module sections for descriptions of behavior in sleep. sleep mode includes the following characteristics: ? the cpu is halted. ? the system clock source is typically shutdown. see section 26.3.3 ?peripheral bus scaling method? for specific information. ? there can be a wake-up delay based on the oscillator selection. ? the fail-safe clock monitor (fscm) does not operate during sleep mode. ? the bor circuit remains operative during sleep mode. ? the wdt, if enabled, is not automatically cleared prior to entering sleep mode. ? some peripherals can cont inue to operate at limited functionality in sleep mode. these peripherals include i/o pins that detect a change in the input signal, wdt, adc, uart and peripherals that use an external clock input or the internal lprc oscillator (e.g., rtcc, timer1 and input capture). ? i/o pins continue to sink or source current in the same manner as they do when the device is not in sleep. ? the usb module can override the disabling of the posc or frc. refer to the usb section for specific details. ? modules can be individually disabled by software prior to entering sleep in order to further reduce consumption. note 1: this data sheet summ arizes the features of the pic32mx330/350/370/430/450/ 470 family of devices. it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 10. ?power- saving features? (ds60001130) in the ?pic32 family reference manual? , which is available from the microchip web site ( www.microchip.com/pic32 ). 2: some registers and associated bits described in this section may not be available on all devices. refer to section 4.0 ?memory organization? in this data sheet for devi ce-specific register and bit information.
pic32mx330/350/370/430/450/470 ds60001185b-page 248 preliminary ? 2012-2013 microchip technology inc. the processor will exit, or ?wake-up?, from sleep on one of the following events: ? on any interrupt from an enabled source that is operating in sleep. the interrupt priority must be greater than the current cpu priority. ? on any form of device reset. ? on a wdt time-out. if the interrupt priority is lower than or equal to the current priority, the cpu will remain halted, but the pbclk will start running and the device will enter into idle mode. 26.3.2 idle mode in idle mode, the cpu is halted but the system clock (sysclk) source is still enabled. this allows peripher - als to continue operation when the cpu is halted. peripherals can be individually configured to halt when entering idle by setting th eir respective sidl bit. latency, when exiting idle mode, is very low due to the cpu oscillator source remaining active. the device enters idle mode when the slpen bit (osccon<4>) is clear and a wait instruction is executed. the processor will wake or exit from idle mode on the following events: ? on any interrupt event for which the interrupt source is enabled. the priority of the interrupt event must be greater than the current priority of the cpu. if the priority of the interrupt event is lower than or equal to curre nt priority of the cpu, the cpu will remain halted and the device will remain in idle mode. ? on any form of device reset ? on a wdt time-out interrupt 26.3.3 peripheral bus scaling method most of the peripherals on the device are clocked using the pbclk. the peripheral bus can be scaled relative to the sysclk to minimize t he dynamic power consumed by the peripherals. the pbcl k divisor is controlled by pbdiv<1:0> (osccon<20:19>), allowing sysclk to pbclk ratios of 1:1, 1:2, 1:4 and 1:8. all peripherals using pbclk are affected when the divisor is changed. peripherals such as the usb, interrupt controller, dma, and the bus matrix are cloc ked directly from sysclk. as a result, they are not affected by pbclk divisor changes. changing the pbclk divisor affects: ? the cpu to peripheral access latency. the cpu has to wait for next pbclk edge for a read to complete. in 1:8 mode, this results in a latency of one to seven sysclks. ? the power consumption of the peripherals. power consumption is directly proportional to the fre - quency at which the peripherals are clocked. the greater the divisor, the lower the power consumed by the peripherals. to minimize dynamic power, the pb divisor should be chosen to run the peripherals at the lowest frequency that provides acceptabl e system performance. when selecting a pbclk divider, peripheral clock require - ments, such as baud rate accuracy, should be taken into account. for example, the uart peripheral may not be able to achieve all baud rate values at some pbclk divider depending on the sysclk value. note 1: changing the pbclk divider ratio requires recalculation of peripheral tim - ing. for example, assume the uart is configured for 9600 baud with a pb clock ratio of 1:1 and a p osc of 8 mhz. when the pb clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. for this reason, any timing cal - culation required for a peripheral should be performed with the new pb clock fre - quency instead of scaling the previous value based on a change in the pb divisor ratio. 2: oscillator start-up and pll lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the pll. for example, assume the clock source is switched from p osc to lprc just prior to entering sleep in order to save power. no oscillator start- up delay would be applied when exiting idle. however, when switching back to p osc , the appropriate pll and/or oscillator start-up/lock delays would be applied.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 249 pic32mx330/350/370/430/450/470 26.4 peripheral module disable the peripheral module disable (pmd) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. when a peripheral is disabl ed using the appropriate pmd control bit, the peripheral is in a minimum power consumption state. the control and status registers associated with the peripheral are also disabled, so writes to those registers do not have effect and read values are invalid. to disable a peripheral, the associated pmdx bit must be set to ? 1 ?. to enable a peripheral, the associated pmdx bit must be cleared (default). see table 26-1 for more information. table 26-1: peripheral module disable bits and locations note: disabling a peripheral module while it?s on bit is set, may result in undefined behavior. the on bit for the associated peripheral module must be cleared prior to disable a module via the pmdx bits. peripheral (1) pmdx bit name (1) register name and bit location adc1 ad1md pmd1<0> ctmu ctmumd pmd1<8> comparator voltage reference cvrmd pmd1<12> comparator 1 cmp1md pmd2<0> comparator 2 cmp2md pmd2<1> input capture 1 ic1md pmd3<0> input capture 2 ic2md pmd3<1> input capture 3 ic3md pmd3<2> input capture 4 ic4md pmd3<3> input capture 5 ic5md pmd3<4> output compare 1 oc1md pmd3<16> output compare 2 oc2md pmd3<17> output compare 3 oc3md pmd3<18> output compare 4 oc4md pmd3<19> output compare 5 oc5md pmd3<20> timer1 t1md pmd4<0> timer2 t2md pmd4<1> timer3 t3md pmd4<2> timer4 t4md pmd4<3> timer5 t5md pmd4<4> uart1 u1md pmd5<0> uart2 u2md pmd5<1> uart3 u3md pmd5<2> uart4 u4md pmd5<3> uart5 u5md pmd5<4> spi1 spi1md pmd5<8> spi2 spi2md pmd5<9> i2c1 i2c1md pmd5<16> i2c2 i2c2md pmd5<17> usb (2) usbmd pmd5<24> rtcc rtccmd pmd6<0> reference clock output refomd pmd6<1> pmp pmpmd pmd6<16> note 1: not all modules and associated pmdx bits are available on all devices. see table 1: ?pic32mx330/350/ 370/430/450/470 controller family features? for the lists of available peripherals. 2: module must not be busy after clearing the associ ated on bit and prior to setting the usbmd bit.
pic32mx330/350/370/430/450/470 ds60001185b-page 250 preliminary ? 2012-2013 microchip technology inc. 26.4.1 controllin g configuration changes because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. pic32 devices include two features to prevent alterations to enabled or disabled peripherals: ? control register lock sequence ? configuration bit select lock 26.4.1.1 control register lock under normal operation, writes to the pmdx registers are not allowed. attempted writes appear to execute normally, but the contents of the registers remain unchanged. to change these registers, they must be unlocked in hardware. the register lock is controlled by the pmdlock configuration bit (cfgcon<12>). set - ting pmdlock prevents writes to the control registers; ? clearing pmdlock allows writes. to set or clear pmdlock, an unlock sequence must be executed. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details. 26.4.1.2 configuratio n bit select lock as an additional level of safety, the device can be configured to prevent more than one write session to the pmdx registers. the pm dl1way configuration bit (devcfg3<28>) blocks the pmdlock bit from being cleared after it has been set once. if pmdlock remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. the only way to clear the bit and re-enable pmd functionality is to perform a device reset.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 251 pic32mx330/350/370/430/450/470 27.0 special features pic32mx330/350/370/430/450/470 devices include several features intended to maximize application flex - ibility and reliability and minimize cost through elimina - tion of external components. these are: ? flexible device configuration ? watchdog timer (wdt) ? joint test action group (jtag) interface ? in-circuit serial programming? (icsp?) 27.1 configuration bits the configuration bits can be programmed using the following registers to se lect various device configurations. ? devcfg0: device configuration word 0 ? devcfg1: device configuration word 1 ? devcfg2: device configuration word 2 ? devcfg3: device configuration word 3 ? cfgcon: configuration control register in addition, the devid register ( register 27-6 ) provides device and revision information. note 1: this data sheet summarizes the features of the pic32mx330/350/370/ 430/450/470 family of devices. however, it is not intended to be a comprehensive reference source. to complement the information in this data sheet, refer to section 9. ?watchdog timer and power-up timer? (ds60001114), section 32. ?configuration? (ds60001124) and section 33. ?programming and diagnostics? (ds60001129) in the ?pic32 family reference manual? , which are available from the microchip web site ( www.microchip.com/pic32 ). register 27-1: devcfg0: d evice configuration word 0 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-0 r-1 r-1 r/p r-1 r-1 r-1 r/p ? ? ?cp ? ? ?bwp 23:16 r-1 r-1 r-1 r-1 r/p r/p r/p r/p ? ? ? ?pwp<7:0> 15:8 r/p r/p r/p r/p r-1 r-1 r-1 r-1 pwp<3:0> ? ? ? ? 7:0 r-1 r-1 r-1 r/p r/p r/p r/p r/p ? ? ? icesel<1:0> jtagen (1) debug<1:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 reserved: write ? 0 ? bit 30-29 reserved: write ? 1 ? bit 28 cp: code-protect bit prevents boot and program flash memory from being read or modified by an external pro- gramming device. 1 = protection is disabled 0 = protection is enabled bit 27-25 reserved: write ? 1 ? note 1: this bit sets the value for the jt agen bit in the cfgcon register.
pic32mx330/350/370/430/450/470 ds60001185b-page 252 preliminary ? 2012-2013 microchip technology inc. bit 24 bwp: boot flash write-protect bit prevents boot flash memory from bei ng modified during code execution. 1 = boot flash is writable 0 = boot flash is not writable bit 23-20 reserved: write ? 1 ? bit 19-12 pwp<7:0>: program flash write-protect bits prevents selected program flash memory pages from being modified during code execution. the pwp bits represent the one?s compliment of the number of write protected program flash memory pages. 11111111 = disabled 11111110 = 0xbd00_0fff 11111101 = 0xbd00_1fff 11111100 = 0xbd00_2fff 11111011 = 0xbd00_3fff 11111010 = 0xbd00_4fff 11111001 = 0xbd00_5fff 11111000 = 0xbd00_6fff 11110111 = 0xbd00_7fff 11110110 = 0xbd00_8fff 11110101 = 0xbd00_9fff 11110100 = 0xbd00_afff 11110011 = 0xbd00_bfff 11110010 = 0xbd00_cfff 11110001 = 0xbd00_dfff 11110000 = 0xbd00_efff 11101111 = 0xbd00_ffff . . . 01111111 = 0xbd07_ffff bit 11-5 reserved: write ? 1 ? bit 4-3 icesel<1:0>: in-circuit emulator/debugger communication channel select bits 11 = pgec1/pged1 pair is used 10 = pgec2/pged2 pair is used 01 = pgec3/pged3 pair is used 00 = reserved bit 2 jtagen: jtag enable bit (1) 1 = jtag is enabled 0 = jtag is disabled bit 1-0 debug<1:0>: background debugger enable bits (forced to ? 11 ? if code-protect is enabled) 1x = debugger is disabled 0x = debugger is enabled register 27-1: devcfg0: device configuration word 0 (continued) note 1: this bit sets the value for the jt agen bit in the cfgcon register.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 253 pic32mx330/350/370/430/450/470 register 27-2: devcfg1: d evice configuration word 1 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r-1 r-1 r-1 r-1 r-1 r/p r/p ? ? ? ? ? ? fwdtwinsz<1:0> 23:16 r/p r/p r-1 r/p r/p r/p r/p r/p fwdten windis ? wdtps<4:0> 15:8 r/p r/p r/p r/p r-1 r/p r/p r/p fcksm<1:0> fpbdiv<1:0> ? osciofnc poscmod<1:0> 7:0 r/p r-1 r/p r-1 r-1 r/p r/p r/p ieso ? fsoscen ? ?fnosc<2:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-26 reserved: write ? 1 ? bit 25-24 fwdtwinsz: watchdog timer window size bits 11 = window size is 25% 10 = window size is 37.5% 01 = window size is 50% 00 = window size is 75% bit 23 fwdten: watchdog timer enable bit 1 = watchdog timer is enabled and cannot be disabled by software 0 = watchdog timer is not enabled; it can be enabled in software bit 22 windis: watchdog timer window enable bit 1 = watchdog timer is in non-window mode 0 = watchdog timer is in window mode bit 21 reserved: write ? 1 ? bit 20-16 wdtps<4:0>: watchdog timer postscale select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 all other combinations not shown result in operation = 10100 note 1: do not disable the p osc (poscmod = 11 ) when using this oscillator source.
pic32mx330/350/370/430/450/470 ds60001185b-page 254 preliminary ? 2012-2013 microchip technology inc. bit 15-14 fcksm<1:0>: clock switching and monitor selection configuration bits 1x = clock switching is disabled, fail-safe clock monitor is disabled 01 = clock switching is enabled, fail-safe clock monitor is disabled 00 = clock switching is enabled, fail-safe clock monitor is enabled bit 13-12 fpbdiv<1:0>: peripheral bus clock divisor default value bits 11 = pbclk is sysclk divided by 8 10 = pbclk is sysclk divided by 4 01 = pbclk is sysclk divided by 2 00 = pbclk is sysclk divided by 1 bit 11 reserved: write ? 1 ? bit 10 osciofnc: clko enable configuration bit 1 = clko output disabled 0 = clko output signal active on the osco pin; prim ary oscillator must be disabled or configured for the external clock mode (ec) for the clko to be active (poscmod<1:0> = 11 or 00 ) bit 9-8 poscmod<1:0>: primary oscillator configuration bits 11 = primary oscillator disabled 10 = hs oscillator mode selected 01 = xt oscillator mode selected 00 = external clock mode selected bit 7 ieso: internal external switchover bit 1 = internal external switchover mode is enabled (two-speed start-up is enabled) 0 = internal external switchover mode is disabled (two-speed start-up is disabled) bit 6 reserved: write ? 1 ? bit 5 fsoscen: secondary oscillator enable bit 1 = enable secondary oscillator 0 = disable secondary oscillator bit 4-3 reserved: write ? 1 ? bit 2-0 fnosc<2:0>: oscillator selection bits 111 = fast rc oscillator with divide-by-n (frcdiv) 110 = frcdiv16 fast rc oscillator with fixed divide-by-16 postscaler 101 = low-power rc oscillator (lprc) 100 = secondary oscillator (s osc ) 011 = primary oscillator (p osc ) with pll module (xt+pll, hs+pll, ec+pll) 010 = primary oscillator (xt, hs, ec) (1) 001 = fast rc oscillator with divi de-by-n with pll module (frcdiv+pll) 000 = fast rc oscillator (frc) register 27-2: devcfg1: device configuration word 1 (continued) note 1: do not disable the p osc (poscmod = 11 ) when using this oscillator source.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 255 pic32mx330/350/370/430/450/470 register 27-3: devcfg2: d evice configuration word 2 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 ? ? ? ? ? ? ? ? 23:16 r-1 r-1 r-1 r-1 r-1 r/p r/p r/p ? ? ? ? ? fpllodiv<2:0> 15:8 r/p r-1 r-1 r-1 r-1 r/p r/p r/p upllen (1) ? ? ? ? upllidiv<2:0> (1) 7:0 r-1 r/p-1 r/p r/p-1 r-1 r/p r/p r/p ? fpllmul<2:0> ? fpllidiv<2:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-19 reserved: write ? 1 ? bit 18-16 fpllodiv<2:0>: default pll output divisor bits 111 = pll output divided by 256 110 = pll output divided by 64 101 = pll output divided by 32 100 = pll output divided by 16 011 = pll output divided by 8 010 = pll output divided by 4 001 = pll output divided by 2 000 = pll output divided by 1 bit 15 upllen: usb pll enable bit (1) 1 = disable and bypass usb pll 0 = enable usb pll bit 14-11 reserved: write ? 1 ? bit 10-8 upllidiv<2:0>: usb pll input divider bits (1) 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider bit 7 reserved: write ? 1 ? bit 6-4 fpllmul<2:0>: pll multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier bit 3 reserved: write ? 1 ? note 1: this bit is available on pic32mx4xx devices only.
pic32mx330/350/370/430/450/470 ds60001185b-page 256 preliminary ? 2012-2013 microchip technology inc. bit 2-0 fpllidiv<2:0>: pll input divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider register 27-3: devcfg2: device configuration word 2 (continued) note 1: this bit is available on pic32mx4xx devices only.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 257 pic32mx330/350/370/430/450/470 register 27-4: devcfg3: d evice configuration word 3 bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 r/p r/p r/p r/p u-0 u-0 u-0 u-0 fvbusonio fusbidi o iol1way pmdl1way ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 r/p r/p r/p ? ? ? ? ? fsrssel<2:0> 15:8 r/p r/p r/p r/p r/p r/p r/p r/p userid<15:8> 7:0 r/p r/p r/p r/p r/p r/p r/p r/p userid<7:0> legend: r = reserved bit p = programmable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31 fvbusonio: usb vbus_on selection bit 1 = v buson pin is controlled by the usb module 0 = v buson pin is controlled by the port function bit 30 fusbidio: usb usbid selection bit 1 = usbid pin is controlled by the usb module 0 = usbid pin is controlled by the port function bit 29 iol1way: peripheral pin select configuration bit 1 = allow only one reconfiguration 0 = allow multiple reconfigurations bit 28 pmdl1way: peripheral module disable configuration bit 1 = allow only one reconfiguration 0 = allow multiple reconfigurations bit 27-19 unimplemented: read as ? 0 ? bit 18-16 fsrssel<2:0>: shadow register set priority select bit these bits assign an interrupt priority to a shadow register. 111 = shadow register set used with interrupt priority 7 110 = shadow register set used with interrupt priority 6 101 = shadow register set used with interrupt priority 5 100 = shadow register set used with interrupt priority 4 011 = shadow register set used with interrupt priority 3 010 = shadow register set used with interrupt priority 2 001 = shadow register set used with interrupt priority 1 000 = shadow register set used with interrupt priority 0 bit 15-0 userid<15:0>: this is a 16-bit value that is user-defined and is readable via icsp? and jtag
pic32mx330/350/370/430/450/470 ds60001185b-page 258 preliminary ? 2012-2013 microchip technology inc. register 27-5: cfgcon: configuration control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 u-0 u-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? ?iolock (1) pmdlock (1) ? ? ? ? 7:0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 u-0 r/w-1 ? ? ? ?jtagentroen ?tdoen legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-14 unimplemented: read as ? 0 ? bit 13 iolock: peripheral pin select lock bit (1) 1 = peripheral pin select is locked. writes to pps registers is not allowed. 0 = peripheral pin select is not locke d. writes to pps re gisters is allowed. bit 12 pmdlock: peripheral module disable bit (1) 1 = peripheral module is locked. writes to pmd registers is not allowed. 0 = peripheral module is not locked. writes to pmd registers is allowed. bit 11-4 unimplemented: read as ? 0 ? bit 3 jtagen: jtag port enable bit 1 = enable the jtag port 0 = disable the jtag port bit 2 troen: trace output enable bit 1 = enable trace outputs and start trac e clock (trace probe must be present) 0 = disable trace outputs and stop trace clock bit 1 unimplemented: read as ? 0 ? bit 0 tdoen: tdo enable for 2-wire jtag 1 = 2-wire jtag protocol uses tdo 0 = 2-wire jtag protocol does not use tdo note 1: to change this bit, the unlock sequence must be performed. refer to section 6. ?oscillator? (ds60001112) in the ?pic32 family reference manual? for details.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 259 pic32mx330/350/370/430/450/470 register 27-6: devid: device and revision id register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 rr r r r r rr ver<3:0> (1) devid<27:24> (1) 23:16 rr r r r r rr devid<23:16> (1) 15:8 rr r r r r rr devid<15:8> (1) 7:0 rr r r r r rr devid<7:0> (1) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-28 ver<3:0>: revision identifier bits (1) bit 27-0 devid<27:0>: device id (1) note 1: see the ?pic32 flash progra mming specification? (ds60001145) for a list of re vision and device id values.
pic32mx330/350/370/430/450/470 ds60001185b-page 260 preliminary ? 2012-2013 microchip technology inc. 27.2 watchdog timer (wdt) this section describes the operation of the wdt and power-up timer of the pic32mx330/350/370/430/450/ 470. the wdt, when enabled, operates from the internal low-power oscillator (lprc) clock source and can be used to detect system softwa re malfunctions by reset - ting the device if the wdt is not cleared periodically in software. various wdt time-out periods can be selected using the wdt postscaler. the wdt can also be used to wake the device from sleep or idle mode. the following are some of t he key features of the wdt module: ? configuration or software controlled ? user-configurable time-out period ? can wake the device from sleep or idle figure 27-1: watchdog and power-up timer block diagram wake wdtclr = 1 wdt enable lprc power save 25-bit counter pwrt enable wdt enable lprc wdt counter reset control oscillator 25 device reset nmi (wake-up) pwrt pwrt enable fwdtps<4:0> (devcfg1<20:16>) clock decoder 1 1:64 output 0 1 wdt enable reset event
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 261 pic32mx330/350/370/430/450/470 register 27-7: wdtcon: watc hdog timer control register bit range bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 31:24 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 23:16 u-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? ? ? 15:8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 on (1,2) ? ? ? ? ? ? ? 7:0 u-0 r-y r-y r-y r-y r-y r/w-0 r/w-0 ? swdtps<4:0> wd twinen wdtclr legend: y = values set from configuration bits on por r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 31-16 unimplemented: read as ? 0 ? bit 15 on: watchdog timer enable bit (1,2) 1 = enables the wdt if it is not enabled by the device configuration 0 = disable the wdt if it was enabled in software bit 14-7 unimplemented: read as ? 0 ? bit 6-2 swdtps<4:0>: shadow copy of watchdog timer postscaler value from device configuration bits on reset, these bits are set to the values of the wdtps <4:0> of configuration bits. bit 1 wdtwinen: watchdog timer window enable bit 1 = enable windowed watchdog timer 0 = disable windowed watchdog timer bit 0 wdtclr: watchdog timer reset bit 1 = writing a ? 1 ? will clear the wdt 0 = software cannot force this bit to a ? 0 ? note 1: a read of this bit results in a ? 1 ? if the watchdog timer is enabled by the device configuration or software. 2: when using the 1:1 pbclk divisor, the user?s software should not read or write the peripheral?s sfrs in the sysclk cycle immediately follo wing the instruction that clears the module?s on bit.
pic32mx330/350/370/430/450/470 ds60001185b-page 262 preliminary ? 2012-2013 microchip technology inc. 27.3 on-chip voltage regulator all pic32mx330/35 0/370/430/450/470 devices? core and digital logic are designed to operate at a nominal 1.8v. to simplify system desi gns, most devices in the pic32mx330/350/370/430/450/4 70 family incorporate an on-chip regulator providing the required core logic voltage from v dd . a low-esr capacitor (such as tantalum) must be connected to the v cap pin (see figure 27-2 ). this helps to maintain the stability of the regulator. the recommended value for the filter capacitor is provided in section 30.1 ?dc characteristics? . 27.3.1 high voltage detect (hvd) the hvd module monitors the core voltage at the v cap pin. if a voltage above the required level is detected on v cap , the i/o pins are disabled and the device is held in reset as long as the hvd condition persists. see parameter hv10 (v hvd ) in ta b l e 30-11 in section 30.1 ?dc characteristics? for more information. 27.3.2 on-chip regulator and por it takes a fixed delay for the on-chip regulator to generate an output. during this time, designated as t pu , code execution is disabled. t pu is applied every time the device resumes operation after any power-down, including sleep mode. 27.3.3 on-chip regulator and bor pic32mx330/350/370/430/450/470 devices also have a simple brown-out capability. if the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator rese t circuitry will generate a brown-out reset. this event is captured by the bor flag bit (rcon<1>). the brown-out voltage levels are specific in section 30.1 ?dc characteristics? . figure 27-2: connections for the on-chip regulator 27.4 programming and diagnostics pic32mx330/350/370/430/45 0/470 devices provide a complete range of programming and diagnostic fea - tures that can increase the flexibility of any application using them. these features allow syst em designers to include: ? simplified field programmability using two-wire ? in-circuit serial pr ogramming? (icsp?) interfaces ? debugging using icsp ? programming and debugging capabilities using the ejtag extension of jtag ? jtag boundary scan testing for device and board diagnostics pic32 devices incorporate two programming and diag - nostic modules, and a trace controller, that provide a range of functions to the application developer. figure 27-3: block diagram of programming, debugging and trace ports note: it is important that the low-esr capacitor is placed as close as possible to the v cap pin. v dd v cap v ss pic32 c efc (2,3) 3.3v (1) note 1: these are typical operating voltages. refer to section 30.1 ?dc characteristics? for the full operating ranges of v dd . 2: it is important that the low-esr capacitor is placed as close as possible to the v cap pin. 3: the typical voltage on the v cap pin is 1.8v. (10 ? f typ) tdi tdo tck tms jtag controller icsp? controller core jtagen debug<1:0> icesel pgec1 pged1 pgec3 pged3 instruction trace controller debug<1:0> trclk trd0 trd2 trd3 trd1
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 263 pic32mx330/350/370/430/450/470 28.0 instruction set the pic32mx330/350/370/430/ 450/470 family instruc - tion set complies with the mips32 ? release 2 instruc - tion set architecture. the pic32 device family does not support the following features: ? core extend instructions ? coprocessor 1 instructions ? coprocessor 2 instructions note: refer to ?mips32 ? architecture for programmers volume ii: the mips32 ? instruction set? at www.mips.com for more information.
pic32mx330/350/370/430/450/470 ds60001185b-page 264 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 265 pic32mx330/350/370/430/450/470 29.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device ? families - hi-tech c ? for various device families - mpasm tm assembler -mplink tm object linker/ ? mplib tm object librarian - mplab assembler/link er/librarian for ? various device families ? simulators - mplab sim software simulator ? emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstratio n/development boards, evaluation kits, and starter kits 29.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based app lication that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select thir d party tools, such as ? iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic32mx330/350/370/430/450/470 ds60001185b-page 266 preliminary ? 2012-2013 microchip technology inc. 29.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control - lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 29.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre - processor, and one-step driver, and can run on multiple platforms. 29.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline ? assembly code ? conditional assembly for multi-purpose ? source files ? directives that allow complete control over the assembly process 29.5 mplink object linker/ ? mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object libraria n manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/libra ry features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 29.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable objec t files that can then be archived or linked with other relocatable object files and archives to create an execut able file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 267 pic32mx330/350/370/430/450/470 29.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat - ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus c ontroller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft - ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi - ronment, making it an excellent, economical software development tool. 29.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerfu l graphical user interface of the mplab integrated devel opment environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-sp eed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 29.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro - chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig - nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon - trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con - nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 29.10 pickit 3 in-circuit debugger/ programmer and ? pickit 3 debug express the mplab pickit 3 allows debugging and program - ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mpl ab integrated development environment (ide). the mpl ab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connec ted to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple - ment in-circuit debugging and in-circuit serial pro - gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software.
pic32mx330/350/370/430/450/470 ds60001185b-page 268 preliminary ? 2012-2013 microchip technology inc. 29.11 pickit 2 development programmer/debugger and ? pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter - face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pi c18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environmen t (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon - trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break - point, the file registers ca n be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 29.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu - lar, detachable socket asse mbly to support various package types. the icsp? ca ble assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc co nnection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporat es an mmc card for file storage and data applications. 29.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demons tration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func - tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, swit ches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picd em? and dspicdem? demon - stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 269 pic32mx330/350/370/430/450/470 30.0 electrical characteristics this section provides an overview of the pic32mx330/350/370/430 /450/470 electrical characteristics. additional information will be provided in future revisions of this document as it becomes available. absolute maximum ratings for the pic32mx330/350/370/430/ 450/470 devices are listed below. exposure to these maximum rating conditions for extended periods may affect devi ce reliability. functional oper ation of the device at these or any other conditions, above the parameters indicated in th e operation listings of this specification, is not implied. absolute maximum ratings (see note 1) ambient temperature under bias................................................................................................. ............-40c to +105c storage temperature ............................................................................................................ .................. -65c to +150c voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +4.0v voltage on any pin that is not 5v tolerant, with respect to v ss (note 3) ......................................... -0.3v to (v dd + 0.3v) voltage on any 5v tolerant pin with respect to v ss when v dd ? 2.3v (note 3) ........................................ -0.3v to +6.0v voltage on any 5v tolerant pin with respect to v ss when v dd < 2.3v (note 3) ........................................ -0.3v to +3.6v voltage on d+ or d- pin with respect to v usb 3 v 3 ..................................................................... -0.3v to (v usb 3 v 3 + 0.3v) voltage on v bus with respect to v ss ....................................................................................................... -0.3v to +5.5v maximum current out of v ss pin(s) .......................................................................................................................2 00 ma maximum current into v dd pin(s) (note 2) ............................................................................................................200 ma maximum output current sourc ed/sunk by any 4x i/o pin .......................................................................... .............15 ma maximum output current sourc ed/sunk by any 8x i/o pin .......................................................................... .............25 ma maximum current sunk by all ports ......................... ..................................................................... .........................150 ma maximum current sourced by all ports (note 2) ....................................................................................................150 ma note 1: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional oper ation of the device at thos e or any other conditions, above those indicated in the operatio n listings of this specification, is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. 2: maximum allowable current is a function of device maximum power dissipation (see table 30-2 ). 3: see the ? pin diagrams ? section for the 5v tolerant pins. 4: all specifications in this sectio n are preliminary, with the exception of the power-down current for pic32mx350/450 devices, which are advance information (see table 30-7 ).
pic32mx330/350/370/430/450/470 ds60001185b-page 270 preliminary ? 2012-2013 microchip technology inc. 30.1 dc characteristics table 30-1: operating mips vs. voltage characteristic v dd range (in volts) temp. range (in c) max. frequency pic32mx330/350/370/430/450/470 dc5 2.3-3.6v (1) -40c to +85c 80 mhz dc5b 2.3-3.6v (1) -40c to +105c 80 mhz note 1: overall functional device operation at v bormin < v dd < v ddmin is tested, but not char acterized. all device analog modules, such as adc, etc., will f unction, but with degraded performance below v ddmin . refer to parameter bo10 in table 30-10 for v bormin values. table 30-2: thermal operating conditions rating symbol min. typical max. unit industrial temperature devices operating junction temperature range t j -40 ? +125 c operating ambient temperature range t a -40 ? +85 c v-temp temperature devices operating junction temperature range t j -40 ? +140 c operating ambient temperature range t a -40 ? +105 c power dissipation: internal chip power dissipation: p int = v dd x (i dd ? s i oh ) p d p int + p i / o w i/o pin power dissipation: i/o = s (({v dd ? v oh } x i oh ) + s (v ol x i ol )) maximum allowed power dissipation p dmax (t j ? t a )/ ? ja w table 30-3: thermal packaging characteristics characteristics symbol typical max. unit notes package thermal resistance , 64-pin qfn (9x9x0.9 mm) ? ja 28 ? c/w 1 package thermal resistance, 64-pin tqfp (10x10x1 mm) ? ja 47 ? c/w 1 package thermal resistance, 100-pin tqfp (12x12x1 mm) ? ja 43 ? c/w 1 package thermal resistance, 100-pin tqfp (14x14x1 mm) ? ja 43 ? c/w 1 package thermal resistance, 124-pin vtla ? ja 21 ? c/w 1 note 1: junction to ambient thermal resistance, theta- ja ( ? ja ) numbers are achieved by package simulations.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 271 pic32mx330/350/370/430/450/470 table 30-4: dc temperature and voltage specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units conditions operating voltage dc10 v dd supply voltage 2.3 ? 3.6 v ? dc12 v dr ram data retention voltage (note 1) 1.75 ? ? v ? dc16 v por v dd start voltage ? to ensure internal ? power-on reset signal 1.75 ? 2.1 v ? dc17 s vdd v dd rise rate ? to ensure internal ? power-on reset signal 0.00005 ? 0.115 v/ ? s? note 1: this is the limit to which v dd can be lowered without losing ram data.
pic32mx330/350/370/430/450/470 ds60001185b-page 272 preliminary ? 2012-2013 microchip technology inc. table 30-5: dc characteristics: operating current (i dd ) dc characteris - tics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp parameter no. typical (3) maximum units conditions operating current (i dd ) (1,2) dc20 2.5 4 ma 4 mhz dc21 6 9 ma 10 mhz (note 4) dc22 11 17 ma 20 mhz (note 4) dc23 21 32 ma 40 mhz (note 4) dc24 30 45 ma 60 mhz (note 4) dc25 40 60 ma 80 mhz dc26 100 ? a +25oc, 3.3v lprc (31 khz) (note 4) note 1: a device?s i dd supply current is mainly a function of the operating voltage and frequency. other factors, such as pbclk (peripheral bus clock) frequency, num ber of peripheral modules enabled, internal code execution pattern, execution from program flash me mory vs. sram, i/o pin loading and switching rate, oscillator type, as well as temperature, c an have an impact on the current consumption. 2: the test conditions for i dd measurements are as follows: ? oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail- to-rail, (osc1 input clock input ov er/undershoot < 100 mv required) ? osc2/clko is configured as an i/o input pin ? usb pll oscillator is disabled if the usb module is implemented, pbclk divisor = 1:8 ? cpu, program flash, and sram data memory are operational, program flash memory wait states = 7, program cache and prefetch are disabled and sram data memory wait states = 1 ? no peripheral modules are operating (on bit = 0 ), but the associated pmd bit is clear ? wdt, clock switching, fail-safe clock moni tor, and secondary oscillator are disabled ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd ? cpu executing while(1) statement from flash ? rtcc and jtag are disabled 3: data in ?typical? column is at 3.3v, 25c at s pecified operating frequency un less otherwise stated. parameters are for design guidance only and are not tested. 4: this parameter is characterized, but not tested in manufacturing.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 273 pic32mx330/350/370/430/450/470 table 30-6: dc characteristics: idle current (i idle ) dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp parameter no. typical (2) maximum units conditions idle current (i idle ): core off, clock on base current (note 1) dc30a 1 2 ma 4 mhz dc31a 3 5 ma 10 mhz (note 3) dc32a 5 7 ma 20 mhz (note 3) dc33a 8 13 ma 40 mhz (note 3) dc34a 11 18 ma 60 mhz (note 3) dc34b 15 24 ma 80 mhz dc37a 100 ? ma -40c 3.3v lprc (31 khz) (note 3) dc37b 250 ? ma +25c dc37c 380 ? ma +85c note 1: the test conditions for i idle measurements are as follows: ? oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail- to-rail, (osc1 input clock input ov er/undershoot < 100 mv required) ? osc2/clko is configured as an i/o input pin ? usb pll oscillator is disabled if the usb module is implemented, pbclk divisor = 1:8 ? cpu is in idle mode (cpu core is halted), prog ram flash memory wait states = 7, program cache and prefetch are disabled and sram data memory wait states = 1 ? no peripheral modules are operating, (on bit = 0 ), but the associated pmd bit is cleared ? wdt, clock switching, fail-safe clock moni tor, and secondary oscillator are disabled ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd ? rtcc and jtag are disabled 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: this parameter is characterized, but not tested in manufacturing.
pic32mx330/350/370/430/450/470 ds60001185b-page 274 preliminary ? 2012-2013 microchip technology inc. table 30-7: dc characteristics: power-down current (i pd ) dc character - istics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. typical (2) maximum units conditions pic32mx330/430 devices only power-down current (i pd ) (note 1) dc40k 12 16 ? a -40c base power-down current dc40l 21 28 ? a +25c dc40n 128 167 ? a +85c dc40m 261 419 a +105oc module differential current dc41e 6.7 ? ? a 3v watchdog timer current: ? i wdt (note 3) dc42e 29.1 ? ? a 3v rtcc + timer1 w/32 khz crystal: ? i rtcc (note 3) dc43d 1000 ? ? a 3v adc: ? i adc (notes 3,4) pic32mx350/450 devices only (note 5) power-down current (i pd ) (note 1) dc40k 12 19 ? a -40c base power-down current dc40l 26 42 ? a +25c dc40n 220 352 ? a +85c dc40m 468 749 a +105oc module differential current dc41e 6.7 ? ? a 3v watchdog timer current: ? i wdt (note 3) dc42e 29.1 ? ? a 3v rtcc + timer1 w/32 khz crystal: ? i rtcc (note 3) dc43d 1000 ? ? a 3v adc: ? i adc (notes 3,4) note 1: the test conditions for i pd measurements are as follows: ? oscillator mode is ec (for 8 mhz and below) and ec+pll (for above 8 mhz) with osc1 driven by external square wave from rail- to-rail, (osc1 input clock input ov er/undershoot < 100 mv required) ? osc2/clko is configured as an i/o input pin ? usb pll oscillator is disabled if the usb module is implemented, pbclk divisor = 1:8 ? cpu is in sleep mode, program flash memory wait states = 7, program cache and prefetch are dis- abled and sram data memory wait states = 1 ? no peripheral modules are operating, (on bit = 0 ), but the associated pmd bit is set ? wdt, clock switching, fail-safe clock moni tor, and secondary oscillator are disabled ? all i/o pins are configured as inputs and pulled to v ss ?mclr = v dd ? rtcc and jtag are disabled ? voltage regulator is off during sleep m ode (vregs bit in the rcon register = 0 ) 2: data in the ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the ? current is the additional current consumed when the module is enabled. this current should be added to the base i pd current. 4: test conditions for adc module differential current ar e as follows: internal adc rc oscillator enabled. 5: the power-down current specifications for pi c32mx350/450 devices is advance information.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 275 pic32mx330/350/370/430/450/470 table 30-8: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2. 3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symb. characteristics min. typ. (1) max. units conditions v il input low voltage di10 i/o pins with pmp v ss ?0.15 v dd v i/o pins v ss ? 0.2 v dd v di18 sdax, sclx v ss ? 0.3 v dd v smbus disabled ? (note 4) di19 sdax, sclx v ss ? 0.8 v smbus enabled ? (note 4) v ih input high voltage di20 i/o pins not 5v-tolerant (5) 0.65 v dd ?v dd v (note 4,6) i/o pins 5v-tolerant with pmp (5) 0.25 v dd + 0.8v ? 5.5 v (note 4,6) i/o pins 5v-tolerant (5) 0.65 v dd ?5.5v di28 sdax, sclx 0.65 v dd ? 5.5 v smbus disabled ? (note 4,6) di29 sdax, sclx 2.1 ? 5.5 v smbus enabled, ? 2.3v ? v pin ? 5.5 ? (note 4,6) di30 i cnpu change noti fication ? pull-up current 50 250 400 ? av dd = 3.3v, v pin = v ss (note 6) di31 i cnpd change noti fication ? pull-down current (4) ?50?av dd = 3.3v, v pin = v dd note 1: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the app lied voltage level. the specified levels represent normal operating co nditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: this parameter is characterized, but not tested in manufacturing. 5: see the ?pin diagrams? section for the 5v tolerant pins. 6: the v ih specifications are only in relation to externa lly applied inputs, and not with respect to the user- selectable internal pull-ups. external open drain inpu t signals utilizing the internal pull-ups of the pic32 device are guaranteed to be recognized only as a logi c ?high? internally to the pic32 device, provided that the external load does not exceed the minimum value of i cnpu . for external ?input? logic inputs that require a pull-up source, to guarantee the minimum v ih of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the pic32 device. 7: v il source < (v ss - 0.3). characterized but not tested. 8: v ih source > (v dd + 0.3) for non-5v tolerant pins only. 9: digital 5v tolerant pins do not have an internal high side diode to v dd , and therefore, cannot tolerate any ?positive? input injection current. 10: injection currents > | 0 | can affect the adc resu lts by approximately 4 to 6 counts (i.e., v ih source > (v dd + 0.3) or v il source < (v ss - 0.3)). 11: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the ?absolute instantaneous? sum of the input inje ction currents from all pins do not exceed the spec- ified limit. if note 7 , i icl = (((vss - 0.3) - v il source) / rs). if note 8 , i ich = ((i ich source - (v dd + 0.3)) / rs). rs = resistance between input source voltage and device pin. if (v ss - 0.3) ? v source ? (v dd + 0.3), injection current = 0 .
pic32mx330/350/370/430/450/470 ds60001185b-page 276 preliminary ? 2012-2013 microchip technology inc. i il input leakage current (note 3) di50 i/o ports ? ? + 1 ? av ss ? v pin ? v dd , ? pin at high-impedance di51 analog input pins ? ? + 1 ? av ss ? v pin ? v dd , ? pin at high-impedance di55 mclr (2) ??+ 1 ? av ss ?? v pin ?? v dd di56 osc1 ? ? + 1 ? av ss ?? v pin ?? v dd , ? xt and hs modes di60a i icl input low injection current 0?-5 (7,10) ma pins with analog functions. exceptions: [n/a] = 0 ma max digital 5v tolerant desig- nated pins. exceptions: ? [n/a] = 0 ma max digital non-5v tolerant desig- nated pins. exceptions: ? [n/a] = 0 ma max table 30-8: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2. 3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symb. characteristics min. typ. (1) max. units conditions note 1: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher le akage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: this parameter is characterized, but not tested in manufacturing. 5: see the ?pin diagrams? section for the 5v tolerant pins. 6: the v ih specifications are only in relation to externa lly applied inputs, and not with respect to the user- selectable internal pull-ups. external open drain inpu t signals utilizing the intern al pull-ups of the pic32 device are guaranteed to be recognized only as a logi c ?high? internally to the pic32 device, provided that the external load does not exceed the minimum value of i cnpu . for external ?input? logic inputs that require a pull-up source, to guarantee the minimum v ih of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the pic32 device. 7: v il source < (v ss - 0.3). characterized but not tested. 8: v ih source > (v dd + 0.3) for non-5v tolerant pins only. 9: digital 5v tolerant pins do not have an internal high side diode to v dd , and therefore, cannot tolerate any ?positive? input injection current. 10: injection currents > | 0 | can affect the adc resu lts by approximately 4 to 6 counts (i.e., v ih source > (v dd + 0.3) or v il source < (v ss - 0.3)). 11: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the ?absolute instantaneous? sum of the input inje ction currents from all pins do not exceed the spec- ified limit. if note 7 , i icl = (((vss - 0.3) - v il source) / rs). if note 8 , i ich = ((i ich source - (v dd + 0.3)) / rs). rs = resistance between input source voltage and device pin. if (v ss - 0.3) ? v source ? (v dd + 0.3), injection current = 0 .
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 277 pic32mx330/350/370/430/450/470 di60b i ich input high injection current 0?+5 (8,9,10) ma pins with analog functions. exceptions: [sosci] = 0 ma max. digital 5v tolerant desig- nated pins (v ih < 5.5v) (9) . exceptions: [all] = 0 ma max. digital non-5v tolerant desig- nated pins. exceptions: ? [n/a] = 0 ma max. di60c ? i ict total input injection current (sum of all i/o and control pins) -20 (11) ?+20 (11) ma absolute instantaneous sum of all input injection cur- rents from all i/o pins ( | i icl + | i ich | ) ? ? i ict table 30-8: dc characteristics: i/o pin input specifications dc characteristics standard operating conditions: 2. 3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symb. characteristics min. typ. (1) max. units conditions note 1: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 2: the leakage current on the mclr pin is strongly dependent on the app lied voltage level. the specified levels represent normal operating co nditions. higher leakage current may be measured at different input voltages. 3: negative current is defined as current sourced by the pin. 4: this parameter is characterized, but not tested in manufacturing. 5: see the ?pin diagrams? section for the 5v tolerant pins. 6: the v ih specifications are only in relation to externa lly applied inputs, and not with respect to the user- selectable internal pull-ups. external open drain inpu t signals utilizing the internal pull-ups of the pic32 device are guaranteed to be recognized only as a logi c ?high? internally to the pic32 device, provided that the external load does not exceed the minimum value of i cnpu . for external ?input? logic inputs that require a pull-up source, to guarantee the minimum v ih of those components, it is recommended to use an external pull-up resistor rather than the internal pull-ups of the pic32 device. 7: v il source < (v ss - 0.3). characterized but not tested. 8: v ih source > (v dd + 0.3) for non-5v tolerant pins only. 9: digital 5v tolerant pins do not have an internal high side diode to v dd , and therefore, cannot tolerate any ?positive? input injection current. 10: injection currents > | 0 | can affect the adc resu lts by approximately 4 to 6 counts (i.e., v ih source > (v dd + 0.3) or v il source < (v ss - 0.3)). 11: any number and/or combination of i/o pins not excluded under i icl or i ich conditions are permitted pro- vided the ?absolute instantaneous? sum of the input inje ction currents from all pins do not exceed the spec- ified limit. if note 7 , i icl = (((vss - 0.3) - v il source) / rs). if note 8 , i ich = ((i ich source - (v dd + 0.3)) / rs). rs = resistance between input source voltage and device pin. if (v ss - 0.3) ? v source ? (v dd + 0.3), injection current = 0 .
pic32mx330/350/370/430/450/470 ds60001185b-page 278 preliminary ? 2012-2013 microchip technology inc. table 30-9: dc characteristics: i/o pin output specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. symbol characteristic mi n. typ. max. units conditions do10 v ol output low voltage i/o pins: 4x sink driver pins - all i/o output pins not defined as 8x sink driver pins ??0.4v i ol ? 9 ma, v dd = 3.3v output low voltage i/o pins: 8x sink driver pins - rc15, rd2, rd10, rf6, rg6 ??0.4vi ol ? 15 ma, v dd = 3.3v do20 v oh output high voltage i/o pins: 4x source driver pins - all i/o output pins not defined as 8x source driver pins 2.4 ? ? v i oh ? -10 ma, v dd = 3.3v output high voltage i/o pins: 8x source driver pins - rc15, rd2, rd10, rf6, rg6 2.4 ? ? v i oh ? -15 ma, v dd = 3.3v do20a v oh 1 output high voltage i/o pins: 4x source driver pins - all i/o output pins not defined as 8x sink driver pins 1.5 (1) ?? v i oh ? -14 ma, v dd = 3.3v 2.0 (1) ?? i oh ? -12 ma, v dd = 3.3v 3.0 (1) ?? i oh ? -7 ma, v dd = 3.3v output high voltage i/o pins: 8x source driver pins - rc15, rd2, rd10, rf6, rg6 1.5 (1) ?? v i oh ? -22 ma, v dd = 3.3v 2.0 (1) ?? i oh ? -18 ma, v dd = 3.3v 3.0 (1) ?? i oh ? -10 ma, v dd = 3.3v note 1: parameters are characterized, but not tested.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 279 pic32mx330/350/370/430/450/470 table 30-10: electrical characteristics: bor dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. (1) typical max. units conditions bo10 v bor bor event on v dd transition high-to-low 2.0 ? 2.3 v ? note 1: parameters are for design guidance only and are not tested in manufacturing. table 30-11: electrical characteristics: hvd dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. (1) symbol characteristics min. typical max. units conditions hv10 v hvd high voltage detect on v cap pin ? 2.5 ? v ? note 1: parameters are for design guidance only and are not tested in manufacturing.
pic32mx330/350/370/430/450/470 ds60001185b-page 280 preliminary ? 2012-2013 microchip technology inc. table 30-12: dc characteristics: program memory dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions program flash memory (3) d130 e p cell endurance 20,000 ? ? e/w ? d131 v pr v dd for read 2.3 ? 3.6 v ? d132 v pew v dd for erase or write 2.3 ? 3.6 v ? d134 t retd characteristic retention 20 ? ? year pr ovided no other specifications are violated d135 i ddp supply current during programming ?10 ?ma ? t ww word write cycle time 44 ? 59 s ? d136 t rw row write cycle time (2) 2.8 3.3 3.8 ms ? d137 t pe page erase cycle time 22 ? 29 ms ? t ce chip erase cycle time 86 ? 116 ms ? note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: the minimum sysclk for row programming is 8 mhz. care should be taken to mi nimize bus activities during row programming, such as suspending any me mory-to-memory dma operations. if heavy bus loads are expected, selecting bus matrix arbitration mode 2 (rotating priority) may be necessary. the default arbitration mode is mode 1 (cpu has lowest priority). 3: refer to the ?pic32 flash progra mming specification? (ds60001145) for operating conditions during programming and erase cycles. table 30-13: dc characteristics: program flash memory wait state dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp required flash wait states sysclk units conditions 0 wait state 0-30 mhz ? 1 wait state 31-60 mhz ? 2 wait states 61-8 0 mhz ?
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 281 pic32mx330/350/370/430/450/470 table 30-14: comparator specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units comments d300 v ioff input offset voltage ? 7.5 25 mv a vdd = v dd , ? a vss = v ss d301 v icm input common mode voltage 0 ? v dd va vdd = v dd , ? a vss = v ss ? (note 2) d302 cmrr common mode rejection ratio 55 ? ? db max v icm = (v dd - 1)v ? (note 2) d303 t resp response time ? 150 400 ns av dd = v dd , ? av ss = v ss ? (notes 1,2) d304 on2 ov comparator enabled to output valid ??10 ? s comparator module is configured before setting the comparator on bit (note 2) d305 iv ref internal voltage reference 1.14 1.2 1.26 v ? d312 t set internal voltage reference setting time (note 3) ??10s ? note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions ? from v ss to v dd . 2: these parameters are characterized but not tested. 3: settling time measured while cvrr = 1 and cvr<3:0> transitions from ? 0000 ? to ? 1111 ?. this parameter is characterized, but not tested in manufacturing. table 30-15: internal voltage regulator specifications dc characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units comments d321 c efc external filter capacitor value 8 10 ? ? f capacitor must be low series resistance (1 ohm). typical voltage on the v cap pin is 1.8v.
pic32mx330/350/370/430/450/470 ds60001185b-page 282 preliminary ? 2012-2013 microchip technology inc. 30.2 ac characteristics and timing parameters the information contained in this section defines pic32mx330/350/370/430/450/4 70 ac characteristics and timing parameters. figure 30-1: load conditions for device timing specifications figure 30-2: external clock timing v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins 50 pf for osc2 pin (ec mode) load condition 1 ? for all pins except osc2 load condition 2 ? for osc2 table 30-16: capacitive loading requirements on output pins ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions do50 c osco osc2 pin ? ? 15 pf in xt and hs modes when an external crystal is used to drive osc1 do56 c io all i/o pins and osc2 ? ? 50 pf ec mode do58 c b sclx, sdax ? ? 400 pf in i 2 c? mode note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. osc1 os20 os30 os30 os31 os31
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 283 pic32mx330/350/370/430/450/470 table 30-17: external clock timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions os10 f osc external clki frequency (external clocks allowed only ? in ec and ecpll modes) dc 4 ? ? 80 80 mhz mhz ec (note 4) ? ecpll (note 3) os11 oscillator crystal frequency 3 ? 10 mhz xt (note 4) os12 4 ? 10 mhz xtpll ? (notes 3,4) os13 10 ? 25 mhz hs (note 5) os14 10 ? 25 mhz hspll ? (notes 3,4) os15 32 32.768 100 khz s osc (note 4) os20 t osc t osc = 1/f osc = t cy (note 2) ? ? ? ? ? see parameter os10 for f osc value os30 t os l, t os h external clock in (osc1) ? high or low time 0.45 x t osc ??nsec (note 4) os31 t os r, t os f external clock in (osc1) ? rise or fall time ? ? 0.05 x t osc ns ec (note 4) os40 t ost oscillator start-up timer period (only applies to hs, hspll, xt, xtpll and s osc clock oscillator modes) ?1024?t osc (note 4) os41 t fscm primary clock fail safe ? time-out period ?2?ms (note 4) os42 g m external oscillator transconductance ?12?ma/vv dd = 3.3v, ? t a = +25c ? (note 4) note 1: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters are characterized but are not tested. 2: instruction cycle period (t cy ) equals the input oscillator time base period. all specified values are based on characterization data for that particular oscillator ty pe under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. 3: pll input requirements: 4 mh z ? f pllin ? 5 mh z (use pll prescaler to reduce f osc ). this parameter is characterized, but tested at 10 mhz only at manufacturing. 4: this parameter is characterized, but not tested in manufacturing.
pic32mx330/350/370/430/450/470 ds60001185b-page 284 preliminary ? 2012-2013 microchip technology inc. table 30-18: pll clock timing specifications ac characteristics standard operating conditions: 2.3v to 3.6v ? (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical max. units conditions os50 f plli pll voltage controlled ? oscillator (vco) input ? frequency range 3.92 ? 5 mhz ecpll, hspll, xtpll, frcpll modes os51 f sys on-chip vco system ? frequency 60 ? 120 mhz ? os52 t lock pll start-up time (lock time) ? ? 2 ms ? os53 d clk clko stability (2) ? (period jitter or cumulative) -0.25 ? +0.25 % measured over 100 ms period note 1: these parameters are characterized, but not tested in manufacturing. 2: this jitter specification is based on clock-cycle by cl ock-cycle measurements. to get the effective jitter for individual time-bases on communicat ion clocks, use t he following formula: for example, if sysclk = 40 mhz and spi bit rate = 20 mhz, the effective jitter is as follows: effectivejitter d clk sysclk communicationclock --------------------------------------------------------- - -------------------------------------------------------------- = effectivejitter d clk 40 20 ----- - ------------- - d clk 1.41 ------------- - == table 30-19: internal frc accuracy ac characteristics standard operating conditions: 2.3v to 3.6v ? (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. characteristics min. typical max. units conditions internal frc accuracy @ 8.00 mhz (1) f20b frc -0.9 ? +0.9 % ? note 1: frequency calibrated at 25c and 3.3v. the tun bits can be used to compensate for temperature drift. table 30-20: internal lprc accuracy ac characteristics standard operating conditions: 2.3v to 3.6v ? (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. characteristics min. typical max. units conditions lprc @ 31.25 khz (1) f21 lprc -15 ? +15 % ? note 1: change of lprc frequency as v dd changes.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 285 pic32mx330/350/370/430/450/470 figure 30-3: i/o timing characteristics note: refer to figure 30-1 for load conditions. i/o pin (input) i/o pin (output) di35 di40 do31 do32 table 30-21: i/o timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (2) min. typical (1) max. units conditions do31 t io r port output rise time ? 5 15 ns v dd < 2.5v ? 5 10 ns v dd > 2.5v do32 t io f port output fall time ? 5 15 ns v dd < 2.5v ? 5 10 ns v dd > 2.5v di35 t inp intx pin high or low time 10 ? ? ns ? di40 t rbp cnx high or low time (input) 2 ? ? t sysclk ? note 1: data in ?typical? column is at 3.3v, 25c unless otherwise stated. 2: this parameter is characterized, but not tested in manufacturing.
pic32mx330/350/370/430/450/470 ds60001185b-page 286 preliminary ? 2012-2013 microchip technology inc. figure 30-4: power-on reset timing characteristics v dd v por note 1: the power-up period will be extended if the power-up sequence completes before the device exits from bor (v dd < v ddmin ). 2: includes interval voltage regulator stabilization delay. sy00 power-up sequence (note 2) internal voltage regulator enabled (t pu ) sy10 cpu starts fetching code clock sources = (hs, h spll, xt, xtpll and s osc ) v dd v por sy00 power-up sequence (note 2) internal voltage regulator enabled (t pu ) (t sysdly ) cpu starts fetching code (note 1) (note 1) clock sources = (frc, frcdiv, frcdi v16, frcpll, ec, ecpll and lprc) (t ost ) sy02 (t sysdly ) sy02
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 287 pic32mx330/350/370/430/450/470 figure 30-5: external reset timing characteristics table 30-22: resets timing ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sy00 t pu power-up period internal voltage regulator enabled ? 400 600 ? s ? sy02 t sysdly system delay period: ? time required to reload device configuration fuses plus sysclk delay before first instruction is fetched. ? ??? s + 8 sysclk cycles ? ? ? sy20 t mclr mclr pulse width (low) 2 ? ? ? s ? sy30 t bor bor pulse width (low) ? 1 ? ? s ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typ? column is at 3.3v, 25c unless otherwise stated. characterized by design but not tested. mclr (sy20) reset sequence (sy10) cpu starts fetching code bor (sy30) t ost t mclr t bor reset sequence cpu starts fetching code clock sources = (frc, f rcdiv, frcdiv16, frcpll , ec, ecpll and lprc) clock sources = (hs, h spll, xt, xtpll and s osc ) (t sysdly ) sy02 (t sysdly ) sy02
pic32mx330/350/370/430/450/470 ds60001185b-page 288 preliminary ? 2012-2013 microchip technology inc. figure 30-6: timer1, 2, 3, 4, 5 ext ernal clock timing characteristics note: refer to figure 30-1 for load conditions. tx11 tx15 tx10 tx20 tmrx os60 txck table 30-23: timer1 external clock timing requirements (1) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (2) min. typical max. units conditions ta10 t tx h txck ? high time synchronous, ? with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ? ns must also meet parameter ta15 asynchronous, ? with prescaler 10 ? ? ns ? ta11 t tx l txck low time synchronous, ? with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ? ns must also meet parameter ta15 asynchronous, ? with prescaler 10 ? ? ns ? ta15 t tx p txck input period synchronous, ? with prescaler [(greater of 25 ns or 2 t pb )/n] + 30 ns ? ? ns v dd > 2.7v [(greater of 25 ns or 2 t pb )/n] + 50 ns ? ? ns v dd < 2.7v asynchronous, ? with prescaler 20 ? ? ns v dd > 2.7v ? (note 3) 50 ? ? ns v dd < 2.7v ? (note 3) os60 f t 1 sosc1/t1ck oscillator input frequency range (oscillator enabled by setting tcs bit (t1con<1>)) 32 ? 100 khz ? ta20 t ckextmrl delay from external txck clock edge to timer ? increment ? 1 t pb ? note 1: timer1 is a type a. 2: this parameter is characterized, but not tested in manufacturing. 3: n = prescale value (1, 8, 64, 256).
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 289 pic32mx330/350/370/430/450/470 figure 30-7: input capture (capx) timing characteristics table 30-24: timer2, 3, 4, 5 external clock timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. max. units conditions tb10 t tx htxck high time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter tb15 n = prescale value ? (1, 2, 4, 8, 16, 32, 64, 256) tb11 t tx ltxck low time synchronous, with prescaler [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter tb15 tb15 t tx ptxck input period synchronous, with prescaler [(greater of [(25 ns or 2 t pb )/n] + 30 ns ?nsv dd > 2.7v [(greater of [(25 ns or 2 t pb )/n] + 50 ns ?nsv dd < 2.7v tb20 t ckextmrl delay from external txck clock edge to timer increment ?1t pb ? note 1: these parameters are characterized, but not tested in manufacturing. icx ic10 ic11 ic15 note: refer to figure 30-1 for load conditions. table 30-25: input capture module timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. max. units conditions ic10 t cc l icx input low time [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter ic15. n = prescale value (1, 4, 16) ic11 t cc h icx input high time [(12.5 ns or 1 t pb )/n] + 25 ns ? ns must also meet parameter ic15. ic15 t cc p icx input period [(25 ns or 2 t pb )/n] + 50 ns ? ns ? note 1: these parameters are characterized, but not tested in manufacturing.
pic32mx330/350/370/430/450/470 ds60001185b-page 290 preliminary ? 2012-2013 microchip technology inc. figure 30-8: output compare module (ocx) timing characteristics table 30-26: output compare module timing requirements figure 30-9: ocx/pwm module timing characteristics ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions oc10 t cc f ocx output fall time ? ? ? ns see parameter do32 oc11 t cc r ocx output rise time ? ? ? ns see parameter do31 note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters ar e for design guidance only and are not tested. ocx oc11 oc10 (output compare note: refer to figure 30-1 for load conditions. or pwm mode) ocfa/ocfb ocx oc20 oc15 note: refer to figure 30-1 for load conditions. ocx is tri-stated table 30-27: simple ocx/pwm mode timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param no. symbol characteristics (1) min typical (2) max units conditions oc15 t fd fault input to pwm i/o change ? ? 50 ns ? oc20 t flt fault input pulse width 50 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless other wise stated. parameters are for design guidance only and are not tested.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 291 pic32mx330/350/370/430/450/470 figure 30-10: spix module master mode (cke = 0 ) timing characteristics table 30-28: spix master mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sp10 t sc l sckx output low time ? (note 3) t sck /2 ? ? ns ? sp11 t sc h sckx output high time ? (note 3) t sck /2 ? ? ns ? sp20 t sc f sckx output fall time ? (note 4) ? ? ? ns see parameter do32 sp21 t sc r sckx output rise time ? (note 4) ? ? ? ns see parameter do31 sp30 t do f sdox data output fall time ? (note 4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time ? (note 4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, ? t sc l2 do v sdox data output valid after sckx edge ? ? 15 ns v dd > 2.7v ? ? 20 ns v dd < 2.7v sp40 t di v2 sc h, ? t di v2 sc l setup time of sdix data input ? to sckx edge 10 ? ? ns ? sp41 t sc h2 di l, ? t sc l2 di l hold time of sdix data input ? to sckx edge 10 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless otherwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. therefor e, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp11 sp10 sp40 sp41 sp21 sp20 sp35 sp20 sp21 msb lsb bit 14 - - - - - -1 msb in lsb in bit 14 - - - -1 sp30 sp31 note: refer to figure 30-1 for load conditions.
pic32mx330/350/370/430/450/470 ds60001185b-page 292 preliminary ? 2012-2013 microchip technology inc. figure 30-11: spix module master mode (cke = 1 ) timing characteristics table 30-29: spix module master mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp10 t sc l sckx output low time (note 3) t sck /2 ? ? ns ? sp11 t sc h sckx output high time (note 3) t sck /2 ? ? ns ? sp20 t sc f sckx output fall time (note 4) ? ? ? ns see parameter do32 sp21 t sc r sckx output rise time (note 4) ? ? ? ns see parameter do31 sp30 t do f sdox data output fall time ? (note 4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time ? (note 4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after ? sckx edge ? ? 15 ns v dd > 2.7v ? ? 20 ns v dd < 2.7v sp36 t do v2 sc , t do v2 sc l sdox data output setup to ? first sckx edge 15 ? ? ns ? sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 15 ? ? ns v dd > 2.7v 20 ? ? ns v dd < 2.7v sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input ? to sckx edge 15 ? ? ns v dd > 2.7v 20 ? ? ns v dd < 2.7v note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. therefor e, the clock generated in master mode must not violate this specification. 4: assumes 50 pf load on all spix pins. sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sdi x sp36 sp30,sp31 sp35 msb bit 14 - - - - - -1 lsb in bit 14 - - - -1 lsb note: refer to figure 30-1 for load conditions. sp11 sp10 sp21 sp20 sp40 sp41 sp20 sp21 msb in
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 293 pic32mx330/350/370/430/450/470 figure 30-12: spix module slave mode (cke = 0 ) timing characteristics ss x sck x (ckp = 0 ) sck x (ckp = 1 ) sdo x sp50 sp40 sp41 sp30,sp31 sp51 sp35 msb lsb bit 14 - - - - - -1 bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp70 note: refer to figure 30-1 for load conditions. sdi x msb in table 30-30: spix module slave mode (cke = 0 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typ. (2) max. units conditions sp70 t sc l sckx input low time (note 3) t sck /2 ? ? ns ? sp71 t sc h sckx input high time (note 3) t sck /2 ? ? ns ? sp72 t sc f sckx input fall time ? ? ? ns see parameter do32 sp73 t sc r sckx input rise time ? ? ? ns see parameter do31 sp30 t do f sdox data output fall time (note 4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time (note 4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after ? sckx edge ? ? 15 ns v dd > 2.7v ? ? 20 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input ? to sckx edge 10 ? ? ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input ? to sckx edge 10 ? ? ns ? sp50 t ss l2 sc h, t ss l2 sc l ssx ? to sckx ? or sckx input 175 ? ? ns ? sp51 t ss h2 do z ssx ? to sdox output ? high-impedance (note 3) 5 ? 25 ns ? sp52 t sc h2 ss h t sc l2 ss h ssx after sckx edge t sck + 20 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless ot herwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. 4: assumes 50 pf load on all spix pins.
pic32mx330/350/370/430/450/470 ds60001185b-page 294 preliminary ? 2012-2013 microchip technology inc. figure 30-13: spix module slave mode (cke = 1 ) timing characteristics ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi sp60 sdix sp30,sp31 msb bit 14 - - - - - -1 lsb sp51 msb in bit 14 - - - -1 lsb in sp52 sp73 sp72 sp72 sp73 sp71 sp40 sp41 note: refer to figure 30-1 for load conditions. sp50 sp70 sp35 table 30-31: spix module slave mode (cke = 1 ) timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions sp70 t sc l sckx input low time (note 3) t sck /2 ? ? ns ? sp71 t sc h sckx input high time (note 3) t sck /2 ? ? ns ? sp72 t sc f sckx input fall time ? 5 10 ns ? sp73 t sc r sckx input rise time ? 5 10 ns ? sp30 t do f sdox data output fall time ? (note 4) ? ? ? ns see parameter do32 sp31 t do r sdox data output rise time ? (note 4) ? ? ? ns see parameter do31 sp35 t sc h2 do v, t sc l2 do v sdox data output valid after ? sckx edge ? ? 20 ns v dd > 2.7v ? ? 30 ns v dd < 2.7v sp40 t di v2 sc h, t di v2 sc l setup time of sdix data input ? to sckx edge 10 ? ? ns ? sp41 t sc h2 di l, t sc l2 di l hold time of sdix data input ? to sckx edge 10 ? ? ns ? sp50 t ss l2 sc h, t ss l2 sc l ssx ? to sckx ? or sckx ? input 175 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. 4: assumes 50 pf load on all spix pins.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 295 pic32mx330/350/370/430/450/470 sp51 t ss h2 do z ssx ? to sdo x output ? high-impedance ? (note 4) 5 ? 25 ns ? sp52 t sc h2 ss h t sc l2 ss h ssx ? after sckx edge t sck + 20 ? ? ns ? sp60 t ss l2 do v sdox data output valid after ? ssx edge ? ? 25 ns ? table 30-31: spix module slave mode (cke = 1 ) timing requirements (continued) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typical (2) max. units conditions note 1: these parameters are characterized, but not tested in manufacturing. 2: data in ?typical? column is at 3.3v, 25c unless othe rwise stated. parameters are for design guidance only and are not tested. 3: the minimum clock period for sckx is 40 ns. 4: assumes 50 pf load on all spix pins.
pic32mx330/350/370/430/450/470 ds60001185b-page 296 preliminary ? 2012-2013 microchip technology inc. figure 30-14: i2cx bus start/stop bits timing characteristics (master mode) figure 30-15: i2cx bus data timing characteristics (master mode) sclx sdax start condition stop condition note: refer to figure 30-1 for load conditions. im30 im31 im34 im33 im11 im10 im33 im11 im10 im20 im26 im25 im40 im40 im45 im21 sclx sdax in sdax out note: refer to figure 30-1 for load conditions.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 297 pic32mx330/350/370/430/450/470 table 30-32: i2cx bus data timing requirements (master mode) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. (1) max. units conditions im10 t lo : scl clock low time 100 khz mode t pb * (brg + 2) ? ? s? 400 khz mode t pb * (brg + 2) ? ? s? 1 mhz mode ? (note 2) t pb * (brg + 2) ? ? s? im11 t hi : scl clock high time 100 khz mode t pb * (brg + 2) ? ? s? 400 khz mode t pb * (brg + 2) ? ? s? 1 mhz mode ? (note 2) t pb * (brg + 2) ? ? s? im20 t f : scl sdax and sclx ? fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ? (note 2) ? 100 ns im21 t r : scl sdax and sclx ? rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ? (note 2) ? 300 ns im25 t su : dat data input ? setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode ? (note 2) 100 ? ns im26 t hd : dat data input ? hold time 100 khz mode 0 ? ? s? 400 khz mode 0 0.9 ? s 1 mhz mode ? (note 2) 0 0.3 ? s im30 t su : sta start condition ? setup time 100 khz mode t pb * (brg + 2) ? ? s only relevant for repeated start ? condition 400 khz mode t pb * (brg + 2) ? ? s 1 mhz mode ? (note 2) t pb * (brg + 2) ? ? s im31 t hd : sta start condition hold time 100 khz mode t pb * (brg + 2) ? ? s after this period, the ? first clock pulse is ? generated 400 khz mode t pb * (brg + 2) ? ? s 1 mhz mode ? (note 2) t pb * (brg + 2) ? ? s im33 t su : sto stop condition setup time 100 khz mode t pb * (brg + 2) ? ? s? 400 khz mode t pb * (brg + 2) ? ? s 1 mhz mode ? (note 2) t pb * (brg + 2) ? ? s im34 t hd : sto stop condition 100 khz mode t pb * (brg + 2) ? ns ? hold time 400 khz mode t pb * (brg + 2) ? ns 1 mhz mode ? (note 2) t pb * (brg + 2) ? ns note 1: brg is the value of the i 2 c? baud rate generator. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: the typical value for this parameter is 104 ns.
pic32mx330/350/370/430/450/470 ds60001185b-page 298 preliminary ? 2012-2013 microchip technology inc. im40 t aa : scl output valid from clock 100 khz mode ? 3500 ns ? 400 khz mode ? 1000 ns ? 1 mhz mode ? (note 2) ? 350 ns ? im45 t bf : sda bus free time 100 khz mode 4.7 ? ? s the amount of time the bus must be free before a new ? transmission can start 400 khz mode 1.3 ? ? s 1 mhz mode ? (note 2) 0.5 ? ? s im50 c b bus capacitive loading ? 400 pf ? im51 t pgd pulse gobbler delay 52 312 ns see note 3 table 30-32: i2cx bus data timing requirements (master mode) (continued) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. (1) max. units conditions note 1: brg is the value of the i 2 c? baud rate generator. 2: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only). 3: the typical value for this parameter is 104 ns.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 299 pic32mx330/350/370/430/450/470 figure 30-16: i2cx bus start/stop bits timing characteristics (slave mode) figure 30-17: i2cx bus data timing characteristics (slave mode) is34 sclx sdax start condition stop condition is33 note: refer to figure 30-1 for load conditions. is31 is30 is30 is31 is33 is11 is10 is20 is26 is25 is40 is40 is45 is21 sclx sdax in sdax out note: refer to figure 30-1 for load conditions.
pic32mx330/350/370/430/450/470 ds60001185b-page 300 preliminary ? 2012-2013 microchip technology inc. table 30-33: i2cx bus data timing requirements (slave mode) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. max. units conditions is10 t lo : scl clock low time 100 khz mode 4.7 ? ? s pbclk must operate at a minimum of 800 khz 400 khz mode 1.3 ? ? s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode ? (note 1) 0.5 ? ? s? is11 t hi : scl clock high time 100 khz mode 4.0 ? ? s pbclk must operate at a minimum of 800 khz 400 khz mode 0.6 ? ? s pbclk must operate at a minimum of 3.2 mhz 1 mhz mode ? (note 1) 0.5 ? ? s? is20 t f : scl sdax and sclx ? fall time 100 khz mode ? 300 ns c b is specified to be from ? 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ? (note 1) ?100ns is21 t r : scl sdax and sclx ? rise time 100 khz mode ? 1000 ns c b is specified to be from ? 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode ? (note 1) ?300ns is25 t su : dat data input ? setup time 100 khz mode 250 ? ns ? 400 khz mode 100 ? ns 1 mhz mode ? (note 1) 100 ? ns is26 t hd : dat data input ? hold time 100 khz mode 0 ? ns ? 400 khz mode 0 0.9 ? s 1 mhz mode ? (note 1) 00.3 ? s is30 t su : sta start condition ? setup time 100 khz mode 4700 ? ns only relevant for repeated start condition 400 khz mode 600 ? ns 1 mhz mode ? (note 1) 250 ? ns is31 t hd : sta start condition hold time 100 khz mode 4000 ? ns after this period, the first clock pulse is generated 400 khz mode 600 ? ns 1 mhz mode ? (note 1) 250 ? ns is33 t su : sto stop condition setup time 100 khz mode 4000 ? ns ? 400 khz mode 600 ? ns 1 mhz mode ? (note 1) 600 ? ns note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only).
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 301 pic32mx330/350/370/430/450/470 is34 t hd : sto stop condition hold time 100 khz mode 4000 ? ns ? 400 khz mode 600 ? ns 1 mhz mode ? (note 1) 250 ns is40 t aa : scl output valid from clock 100 khz mode 0 3500 ns ? 400 khz mode 0 1000 ns 1 mhz mode ? (note 1) 0350ns is45 t bf : sda bus free time 100 khz mode 4.7 ? ? s the amount of time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s 1 mhz mode ? (note 1) 0.5 ? ? s is50 c b bus capacitive loading ? 400 pf ? table 30-33: i2cx bus data timing requirements (slave mode) (continued) ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. max. units conditions note 1: maximum pin capacitance = 10 pf for all i2cx pins (for 1 mhz mode only).
pic32mx330/350/370/430/450/470 ds60001185b-page 302 preliminary ? 2012-2013 microchip technology inc. table 30-34: adc module specifications ac characteristics (5) standard operating conditions: 2.5v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units conditions device supply ad01 av dd module v dd supply greater of v dd ? 0.3 or 2.5 ? lesser of v dd + 0.3 or 3.6 v ? ad02 av ss module v ss supply v ss ?v ss + 0.3 v ? reference inputs ad05 v refh reference voltage high av ss + 2.0 ? av dd v (note 1) ad05a 2.5 ? 3.6 v v refh = av dd (note 3) ad06 v refl reference voltage low av ss ?v refh ? 2.0 v (note 1) ad07 v ref absolute reference voltage (v refh ? v refl ) 2.0 ? av dd v (note 3) ad08 i ref current drain ? 250 ? 400 3 ? a ? a adc operating ? adc off analog input ad12 v inh -v inl full-scale input span v refl ?v refh v? ad13 v inl absolute v inl input voltage av ss ? 0.3 ? av dd /2 v ? ad14 v in absolute input voltage av ss ? 0.3 ? av dd + 0.3 v ? ad15 leakage current ? +/- 0.001 +/-0.610 ? av inl = av ss = v refl = 0v, ? av dd = v refh = 3.3v source impedance = 10 k ? ad17 r in recommended impedance of analog voltage source ??5k ? (note 1) adc accuracy ? measurements with external v ref +/v ref - ad20c nr resolution 10 data bits bits ? ad21c inl integral nonlinearity > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad22c dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v (note 2) ad23c g err gain error > -1 ? < 1 lsb v inl = av ss = v refl = 0v, av dd = v refh = 3.3v ad24n e off offset error > -1 ? < 1 lsb v inl = av ss = 0v, ? av dd = 3.3v ad25c ? monotonicity ? ? ? ? guaranteed note 1: these parameters are not characteri zed or tested in manufacturing. 2: with no missing codes. 3: these parameters are characterized, but not tested in manufacturing. 4: characterized with a 1 khz sine wave. 5: overall functional device operation at v bormin < v dd < v ddmin is tested, but not characterized. all device analog modules, such as adc, etc., will f unction, but with degraded performance below v ddmin . refer to parameter bo10 in table 30-10 for v bormin values.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 303 pic32mx330/350/370/430/450/470 adc accuracy ? measurements with internal v ref +/v ref - ad20d nr resolution 10 data bits bits (note 3) ad21d inl integral nonlinearity > -1 ? < 1 lsb v inl = av ss = 0v, ? av dd = 2.5v to 3.6v ? (note 3) ad22d dnl differential nonlinearity > -1 ? < 1 lsb v inl = av ss = 0v, ? av dd = 2.5v to 3.6v (notes 2,3) ad23d g err gain error > -4 ? < 4 lsb v inl = av ss = 0v, ? av dd = 2.5v to 3.6v ? (note 3) ad24d e off offset error > -2 ? < 2 lsb v inl = av ss = 0v, ? av dd = 2.5v to 3.6v ? (note 3) ad25d ? monotonicity ? ? ? ? guaranteed dynamic performance ad31b sinad signal to noise and ? distortion 55 58 ? db (notes 3,4) ad34b enob effective number of bits 9 9.5 ? bits (notes 3,4) table 30-34: adc module specifications (continued) ac characteristics (5) standard operating conditions: 2.5v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical max. units conditions note 1: these parameters are not characteri zed or tested in manufacturing. 2: with no missing codes. 3: these parameters are characterized, but not tested in manufacturing. 4: characterized with a 1 khz sine wave. 5: overall functional device operation at v bormin < v dd < v ddmin is tested, but not characterized. all device analog modules, such as adc, etc., will f unction, but with degraded performance below v ddmin . refer to parameter bo10 in table 30-10 for v bormin values.
pic32mx330/350/370/430/450/470 ds60001185b-page 304 preliminary ? 2012-2013 microchip technology inc. table 30-35: 10-bit conversion rate parameters ac characteristics (2) standard operating conditions: 2.5v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp adc input adc speed t ad min. sampling time min. r s max. v dd adc channels configuration an0-an14 1 msps to 400 ksps (1) 65 ns 132 ns 500 ? 3.0v to 3.6v up to 400 ksps 200 ns 200 ns 5.0 k ? 2.5v to 3.6v an15-an27 400 ksps (1) 154 ns 1000 ns 500 ? 3.0v to 3.6v note 1: external v ref - and v ref + pins must be used for correct operation. 2: these parameters are characterized, but not tested in manufacturing. v ref -v ref + adc anx sha ch x v ref -v ref + adc anx sha ch x anx or v ref - or av ss or av dd v ref -v ref + adc anx sha ch x
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 305 pic32mx330/350/370/430/450/470 table 30-36: analog-to-digital co nversion timing requirements ac characteristics standard operating conditions: 2.5v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics min. typical (1) max. units conditions clock parameters ad50 t ad adc clock period (2) 65 ? ? ns see table 30-35 conversion rate ad55 tconv conversion time ? 12 t ad ?? ? ad56 f cnv throughput rate ? (sampling speed) (4) ? ? 1000 ksps av dd = 3.0v to 3.6v ? ? 400 ksps av dd = 2.5v to 3.6v ad57 t samp sample time 1 t ad ???t samp must be ? 132 ns timing parameters ad60 tpcs conversion start from sample ? trigger (3) ?1.0 t ad ? ? auto-convert trigger (ssrc<2:0> = 111 ) not selected ad61 tpss sample start from setting ? sample (samp) bit 0.5 t ad ? 1.5 t ad ?? ad62 tcss conversion completion to ? sample start (asam = 1 ) (3) ?0.5 t ad ?? ? ad63 tdpu time to stabilize analog stage ? from adc off to adc on (3) ?? 2 ? s? note 1: these parameters are characterized, but not tested in manufacturing. 2: because the sample caps will eventually lose char ge, clock rates below 10 khz can affect linearity performance, especially at elevated temperatures. 3: characterized by design but not tested. 4: refer to table 30-35 for detailed conditions.
pic32mx330/350/370/430/450/470 ds60001185b-page 306 preliminary ? 2012-2013 microchip technology inc. figure 30-18: analog-to-digital co nversion (10-bit mode) timing characteristics (asam = 0 , ssrc<2:0> = 000 ) ad55 t samp clear samp set samp ad61 adclk instruction samp ch0_dischrg ad60 conv adxif buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 8 5 6 7 1 ? software sets adxcon. samp to start sampling. 2 ? sampling starts after discharge period. t samp is described in section 17. ?10-bit analog-to-digital converter (adc)? 3 ? software clears adxcon. samp to start conversion. 4 ? sampling ends, conversion sequence starts. 5 ? convert bit 9. 8 ? one t ad for end of conversion. ad50 ch0_samp eoc 7 ad55 8 6 ? convert bit 8. 7 ? convert bit 0. execution (ds60001104) in the ?pic32 family reference manual? .
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 307 pic32mx330/350/370/430/450/470 figure 30-19: analog-to-digital conversion (10-bit mode) timing characteristics (asam = 1 , ssrc<2:0> = 111 , samc<4:0> = 00001 ) ad55 t samp set adon adclk instruction samp ch0_dischrg conv adxif buffer( 0 ) buffer( 1 ) 1 2 3 4 5 6 4 5 6 8 1 ? software sets adxcon. adon to start ad operation. 2 ? sampling starts after discharge period. 3 ? convert bit 9. 4 ? convert bit 8. 5 ? convert bit 0. ad50 ch0_samp eoc 7 3 ad55 6 ? one t ad for end of conversion. 7 ? begin conversion of next channel. 8 ? sample for time specified by samc<4:0>. t samp t conv 3 4 execution t samp is described in section 17. ?10-bit analog-to-digital converter (adc)? (ds60001104) in the ?pic32 family reference manual ?
pic32mx330/350/370/430/450/470 ds60001185b-page 308 preliminary ? 2012-2013 microchip technology inc. figure 30-20: parallel slave port timing cs rd wr pmd<7:0> ps1 ps2 ps3 ps4 ps5 ps6 ps7 table 30-37: parallel slave port requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp para m.no. symbol characteristics (1) min. typ. max. units conditions ps1 tdtv2wr h data in valid before wr or cs inactive (setup time) 20 ? ? ns ? ps2 twrh2dt i wr or cs inactive to data-in invalid (hold time) 40 ? ? ns ? ps3 trdl2dt v rd and cs active to data-out valid ? ? 60 ns ? ps4 trdh2dti rd active ? or cs inactive to data-out invalid 0 ? 10 ns ? ps5 tc s cs active time t pb + 40 ? ? ns ? ps6 t wr wr active time t pb + 25 ? ? ns ? ps7 t rd rd active time t pb + 25 ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 309 pic32mx330/350/370/430/450/470 figure 30-21: parallel master port read timing diagram t pb t pb t pb t pb t pb t pb t pb t pb pb clock pmall/pmalh pmd<7:0> pma<13:18> pmrd pmcs<2:1> pmwr pm5 data address<7:0> pm1 pm3 pm6 data pm7 address<7:0> address pm4 pm2 table 30-38: parallel master port read timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typ. max. units conditions pm1 t lat pmall/pmalh pulse width ? 1 t pb ? ? ? pm2 t adsu address out valid to pmall/ pmalh invalid (address setup time) ? 2 t pb ? ? ? pm3 t adhold pmall/pmalh invalid to address out invalid (address hold time) ? 1 t pb ? ? ? pm4 t ahold pmrd inactive to address out invalid (address hold time) 5 ? ? ns ? pm5 t rd pmrd pulse width ? 1 t pb ? ? ? pm6 t dsu pmrd or pmenb active to data in valid (data setup time) 15 ? ? ns ? pm7 t dhold pmrd or pmenb inactive to data in invalid (data hold time) ? 8 0 ? ns ? note 1: these parameters are characterized, but not tested in manufacturing.
pic32mx330/350/370/430/450/470 ds60001185b-page 310 preliminary ? 2012-2013 microchip technology inc. figure 30-22: parallel master port write timing diagram t pb t pb t pb t pb t pb t pb t pb t pb pb clock pmall/pmalh pmd<7:0> pma<13:18> pmwr pmcs<2:1> pmrd pm12 pm13 pm11 address address<7:0> data pm2 + pm3 pm1 table 30-39: parallel master po rt write timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typ. max. units conditions pm11 t wr pmwr pulse width ? 1 t pb ? ? ? pm12 t dvsu data out valid before pmwr or pmenb goes inactive (data setup time) ? 2 t pb ? ? ? pm13 t dvhold pmwr or pmemb invalid to data out invalid (data hold time) ? 1 t pb ? ? ? note 1: these parameters are characterized, but not tested in manufacturing.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 311 pic32mx330/350/370/430/450/470 table 30-40: otg electrical specifications ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol characteristics (1) min. typ. max. units conditions usb313 v usb 3 v 3 usb voltage 3.0 ? 3.6 v voltage on v usb 3 v 3 must be in this range for proper usb operation usb315 v ilusb input low voltage for usb buffer ? ? 0.8 v ? usb316 v ihusb input high voltage for usb buffer 2.0 ? ? v ? usb318 v difs differential input sensitivity ? ? 0.2 v the difference between d+ and d- must exceed this value while vcm is met usb319 vcm differential common mode range 0.8 ? 2.5 v ? usb320 z out driver output impedance 28.0 ? 44.0 ? ? usb321 v ol voltage output low 0.0 ? 0.3 v 14.25 k ? load connected to 3.6v usb322 v oh voltage output high 2.8 ? 3.6 v 14.25 k ? load connected to ground note 1: these parameters are characterized, but not tested in manufacturing.
pic32mx330/350/370/430/450/470 ds60001185b-page 312 preliminary ? 2012-2013 microchip technology inc. table 30-41: ctmu current source specifications dc characteristics standard oper ating conditions :2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param no. symbol characteristic min. typ. max. units conditions ctmu c urrent s ource ctmui1 i out 1 base range (1) ? 0.55 ? a ctmuicon<9:8> = 01 ctmui2 i out 2 10x range (1) ? 5.5 ? a ctmuicon<9:8> = 10 ctmui3 i out 3 100x range (1) ? 55 ? a ctmuicon<9:8> = 11 ctmui4 i out 4 1000x range (1) ? 550 ? a ctmuicon<9:8> = 00 ctmufv1 v f temperature diode forward voltage (1,2) ?0.598? vt a = +25oc, ? ctmuicon<9:8> = 01 ?0.658? vt a = +25oc, ? ctmuicon<9:8> = 10 ?0.721? vt a = +25oc, ? ctmuicon<9:8> = 11 ctmufv2 v fvr temperature diode rate of change (1,2) ? -1.92 ? mv/oc ctmuicon<9:8> = 01 ? -1.74 ? mv/oc ctmuicon<9:8> = 10 ? -1.56 ? mv/oc ctmuicon<9:8> = 11 note 1: nominal value at center point of cu rrent trim range (ctmuicon<15:10> = 000000 ). 2: parameters are characterized but not tested in m anufacturing. measurements taken with the following conditions: ?v ref + = av dd = 3.3v ? adc module configured for c onversion speed of 500 ksps ? all pmd bits are cleared (pmdx = 0 ) ? executing a while(1) statement ? device operating from the frc with no pll
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 313 pic32mx330/350/370/430/450/470 figure 30-23: ejtag timing characteristics t tckeye t tckhigh t tcklow t rf t rf t rf t rf t tsetup t thold t tdoout t tdozstate defined undefined t trst*low t rf tck tdo trst* tdi tms table 30-42: ejtag timing requirements ac characteristics standard operating conditions: 2.3v to 3.6v (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial ? -40c ? t a ? +105c for v-temp param. no. symbol description (1) min. max. units conditions ej1 t tckcyc tck cycle time 25 ? ns ? ej2 t tckhigh tck high time 10 ? ns ? ej3 t tcklow tck low time 10 ? ns ? ej4 t tsetup tap signals setup time before rising tck 5 ? ns ? ej5 t thold tap signals hold time after rising tck 3 ? ns ? ej6 t tdoout tdo output delay time from falling tck ? 5 ns ? ej7 t tdozstate tdo 3-state delay time from falling tck ? 5 ns ? ej8 t trstlow trst low time 25 ? ns ? ej9 t rf tap signals rise/fall time, all input and output ? ? ns ? note 1: these parameters are characterized, but not tested in manufacturing.
pic32mx330/350/370/430/450/470 ds60001185b-page 314 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 315 pic32mx330/350/370/430/450/470 31.0 dc and ac device characteristics graphs figure 31-1: v oh ? 4x driver pins figure 31-2: v oh ? 8x driver pins figure 31-3: v ol ? 4x driver pins figure 31-4: v ol ? 8x driver pins note: the graphs provided following this note ar e a statistical summary based on a limited number of samples and are provided for des ign guidance purposes only. the performance characteristics listed herein are not test ed or guaranteed. in some graphs, the data presented may be out side the specified operating range (e.g., outside specified power supply rang e) and therefore, outsi de the warranted range. r 40.00 r 35.00 r 30.00 r 25.00 r 20.00 r 15.00 current (ma) r 10.00 r 5.00 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 voltage (v) 3.3v asolutemaimum r 70.00 r 60.00 r 50.00 r 40.00 r 30.00 current (ma) r 20.00 r 10.00 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 voltage (v) 3.3v asolutemaimum 15.000 20.000 25.000 30.000 35.000 40.000 45.000 current (ma) 0.000 5.000 10.000 0.000 0.500 1.000 1.500 2.000 2.500 3.000 voltage (v) 3.3v asolutemaimum 30.000 40.000 50.000 60.000 70.000 80.000 current (ma) 0.000 10.000 20.000 0.000 0.500 1.000 1.500 2.000 2.500 3.000 voltage (v) 3.3v asolutemaimum
pic32mx330/350/370/430/450/470 ds60001185b-page 316 preliminary ? 2012-2013 microchip technology inc. figure 31-5: typical i pd current @ v dd = 3.3v figure 31-6: typical i pd current @ v dd = 3.3v figure 31-7: typical i idle current @ v dd = 3.3v figure 31-8: typical i idle current @ v dd = 3.3v pic32mx330/430 devices 150 200 250 300 350 400 i pd (a) 0 50 100 150 r 40 r 30 r 20 r 100 102030405060708090100 temperature (celsius) 200 250 300 350 400 450 500 i pd (a) 0 50 100 150 r 40 r 30 r 20 r 100 102030405060708090100 temperature (celsius) pic32mx350/450 devices pic32mx330/430 devices 6 8 10 12 14 16 current (ma) 0 2 4 6 0 1020304050607080 i idle mips pic3m350450devices 6 8 10 12 14 16 current (ma) 0 2 4 6 0 1020304050607080 i idle mips
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 317 pic32mx330/350/370/430/450/470 figure 31-9: typical i dd current @ v dd = 3.3v figure 31-10: typical i dd current @ v dd = 3.3v figure 31-11: typical frc frequency @ v dd = 3.3v figure 31-12: typical lprc frequency @ v dd = 3.3v pic32mx330/430 devices 20 25 30 35 40 45 i dd (ma) 0 5 10 15 0 1020304050607080 mips pic3m350450devices 20 25 30 35 40 45 i dd (ma) 0 5 10 15 0 1020304050607080 mips 7930 7940 7950 7960 7970 7980 7990 8000 frc frequency (khz) 7900 7910 7920 7930 7940 7950 7960 7970 7980 7990 8000 -40-30-20-10 0 102030405060708090100 frc frequency (khz) temperature (celsius) 31 32 33 lprc frequency (khz) 30 31 32 33 -40-30-20-10 0 102030405060708090100 lprc frequency (khz) temperature (celsius)
pic32mx330/350/370/430/450/470 ds60001185b-page 318 preliminary ? 2012-2013 microchip technology inc. figure 31-13: typical ctmu temperature diode forward voltage 0500 0.550 0.600 0.650 0.700 0.750 0.800 0.850 forward voltage (v) 0.350 0.400 0.450 0.500 0.550 0.600 0.650 0.700 0.750 0.800 0.850 -40-30-20-100 102030405060708090100110 forward voltage (v) temperature (celsius) v f = 0.598 v f = 0.658 v f = 0.721 55 a , v f v r = - 1 . 5 6 m v / o c 5 . 5 a , v f v r = - 1 . 7 4 m v / o c 0 . 5 5 a , v f v r = - 1 . 9 2 m v / o c
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 319 pic32mx330/350/370/430/450/470 32.0 packaging information 32.1 package marking information pic32mx330f 064h-i/pt 0510017 3 e legend: xx...x customer-specific information ? y year code (last digit of calendar year) ? yy year code (last 2 digits of calendar year) ? ww week code (week of january 1 is week ?01?) ? nnn alphanumeric traceability code ? pb-free jedec designator for matte tin (sn) ? * this package is pb-free. the pb-free jedec designator ( ) ? can be found on the outer packaging for this package. note: in the event the full microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for customer-specific information. 3 e 64-lead tqfp (10x10x1 mm) xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example 100-lead tqfp (12x12x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic32mx330f 064l-i/pt 0510017 3 e 100-lead tqfp (14x14x1 mm) xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic32mx330f 064l-i/pf 0510017 3 e
pic32mx330/350/370/430/450/470 ds60001185b-page 320 preliminary ? 2012-2013 microchip technology inc. 32.1 package marking information (continued) xxxxxxxxxx 64-lead qfn (9x9x0.9 mm) xxxxxxxxxx xxxxxxxxxx yywwnnn pic32mx330f example 064h-i/mr 0510017 3 e xxxxxxxxxx 124-lead vtla (9x9x0.9 mm) xxxxxxxxxx xxxxxxxxxx yywwnnn pic32mx430f example 064l-i/tl 0510017 3 e legend: xx...x customer-specific information ? y year code (last digit of calendar year) ? yy year code (last 2 digits of calendar year) ? ww week code (week of january 1 is week ?01?) ? nnn alphanumeric traceability code ? pb-free jedec designator for matte tin (sn) ? * this package is pb-free. the pb-free jedec designator ( ) ? can be found on the outer packaging for this package. note: in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 321 pic32mx330/350/370/430/450/470 32.2 package details the following sections give the technical details of the packages.

!" #$ %
& ' ( !"# $% &" ' ()"&'"!&) & #*&& & # +'% !& !
&,!- ' ' !!#.#&"# '#%!
&"!!#%!
&"!!!& $ #/''
!# ' !#&
.0/ 1+2 1!' ! & $& " !**&"&& ! .32 % ' !("!"*&"&& (%%'&
"
! ! ' ( 3& '!&" &
4 #*!(
! ! &
4
%&& #& &&
255***'
'5
4 6&! 77.. ' !7'&! 8 89 : 8"') %7 #! 8 ; 7 #& /1+ 9 < & = = # #4 4 !! / / &#%% / = / 3&7 & 7 / ; / 3&
& 7 .3 3& > /> > 9 ?#& . 1+ 9 7 & 1+ # #4 ?#& . 1+ # #4 7 & 1+ 7 #4 !! = 7 #?#& ) #%&
> > > #%& 1&&' > > > d d1 e e1 e b n note 1 123 note 2 c l a1 l1 a2 a
* + @/1
pic32mx330/350/370/430/450/470 ds60001185b-page 322 preliminary ? 2012-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 323 pic32mx330/350/370/430/450/470

!" #$ %
& ' ( !"# $% &" ' ()"&'"!&) & #*&& & # +'% !& !
&,!- ' ' !!#.#&"# '#%!
&"!!#%!
&"!!!& $ #/''
!# ' !#&
.0/ 1+2 1!' ! & $& " !**&"&& ! .32 % ' !("!"*&"&& (%%'&
"
! ! ' ( 3& '!&" &
4 #*!(
! ! &
4
%&& #& &&
255***'
'5
4 6&! 77.. ' !7'&! 8 89 : 8"') %7 #! 8 7 #& /1+ 9 < & = = # #4 4 !! / / &#%% / = / 3&7 & 7 / ; / 3&
& 7 .3 3& > /> > 9 ?#& . ;1+ 9 7 & ;1+ # #4 ?#& . 1+ # #4 7 & 1+ 7 #4 !! = 7 #?#& ) #%&
> > > #%& 1&&' > > > d d1 e b e1 e n note 1 note 2 123 c l a1 l1 a2 a
* + 1
pic32mx330/350/370/430/450/470 ds60001185b-page 324 preliminary ? 2012-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 325 pic32mx330/350/370/430/450/470

## !" #$ %
& ' ( !"# $% &" ' ()"&'"!&) & #*&& & # +'% !& !
&,!- ' ' !!#.#&"# '#%!
&"!!#%!
&"!!!& $ #/''
!# ' !#&
.0/ 1+2 1!' ! & $& " !**&"&& ! .32 % ' !("!"*&"&& (%%'&
"
! ! ' ( 3& '!&" &
4 #*!(
! ! &
4
%&& #& &&
255***'
'5
4 6&! 77.. ' !7'&! 8 89 : 8"') %7 #! 8 7 #& 1+ 9 < & = = # #4 4 !! / / &#%% / = / 3&7 & 7 / ; / 3&
& 7 .3 3& > /> > 9 ?#& . 1+ 9 7 & 1+ # #4 ?#& . 1+ # #4 7 & 1+ 7 #4 !! = 7 #?#& ) @ #%&
> > > #%& 1&&' > > > d d1 e e1 e b n 123 note 1 note 2 c l a1 l1 a a2
* + 1
pic32mx330/350/370/430/450/470 ds60001185b-page 326 preliminary ? 2012-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 327 pic32mx330/350/370/430/450/470 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic32mx330/350/370/430/450/470 ds60001185b-page 328 preliminary ? 2012-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 329 pic32mx330/350/370/430/450/470 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic32mx330/350/370/430/450/470 ds60001185b-page 330 preliminary ? 2012-2013 microchip technology inc.
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 331 pic32mx330/350/370/430/450/470
pic32mx330/350/370/430/450/470 ds60001185b-page 332 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 333 pic32mx330/350/370/430/450/470 appendix a: revision history revision a (july 2012) this is the initial releas ed version of the document. revision b (april 2013) this revision includes the following updates, as shown in table a-1 . note: the status of this data sheet was updated to preliminary; however, any electrical specifications listed for pic32mx370/470 devices is to be considered advance information and is marked accordingly. table a-1: major section updates section update description ? 32-bit microcontro llers (up to 512 kb flash and 128 kb sram) with audio/graphics/touch (hmi), usb, and advanced analog ? sram was changed from 32 kb to 64 kb. data memory (kb) was changed from 32 to 64 for the following devices (see ta b l e 1 ): ? pic32mx350f256h ? pic32mx350f256l ? pic32mx450f256h ? pic32mx450f256l the following devices were added: ? pic32mx370f512h ? pic32mx370f512l ? PIC32MX470F512H ? pic32mx470f512l 4.0 ?memory organization? the memory map for devices with 256 kb of program memory was updated (see figure 4-3 ). the memory map for devices with 512 kb of program memory was added (see figure 4-4 ). 7.0 ?interrupt controller? updated the interrupt irq, vector and bit locations (see ta b l e 7-1 ). 20.0 ?parallel master port (pmp)? added the cs2 bit and updated the addr bits in the parallel port address register (see register 20-3 ). 27.0 ?special features? updated the pwp bit in the device co nfiguration word 3 register (see register 27-4 ). 30.0 ?electrical characteristics? note 2 in the dc characteristics: operating current (i dd ) were updated (see ta b l e 30-5 ). note 1 in the dc characteristics: idle current (i idle ) were updated (see ta b l e 30-6 ). note 1 in the dc characteristics: power-down current (i pd ) were updated (see ta b l e 30-7 ). updated program memory values for parameters d135 (t ww ), d136 (t rw ), and d137 (t pe and t ce ) (see table 30-12 ). 31.0 ?dc and ac device characteristics graphs? new i dd , i idle , and i pd current graphs were added for pic32mx330/430 devices and pic32m x350/450 devices.
pic32mx330/350/370/430/450/470 ds60001185b-page 334 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 335 pic32mx330/350/370/430/450/470 index a ac characteristics ............................................................ 282 10-bit conversion rate parameters ......................... 304 adc specifications ................................................... 302 analog-to-digital conversion requirements............. 305 ejtag timing requirements ................................... 313 internal frc accuracy.............................................. 284 internal rc accuracy ................................................ 284 otg electrical specifications ................................... 311 parallel master port read requirements ................. 309 parallel master port write ......................................... 310 parallel master port write requirements.................. 310 parallel slave port requirements ............................. 308 pll clock timing...................................................... 284 analog-to-digital converter (adc).................................... 229 assembler mpasm assembler................................................... 266 b block diagrams adc module.............................................................. 229 comparator i/o operating modes............................. 237 comparator voltage reference ................................ 241 connections for on-chip voltage regulator............. 262 cpu ............................................................................ 33 ctmu configurations time measurement ........................................... 243 dma .......................................................................... 129 i2c circuit ................................................................. 200 input capture ............................................................ 185 interrupt controller .................................................... 101 jtag programming, debugging and trace ports .... 262 output compare module........................................... 189 pmp pinout and connections to external devices ... 211 prefetch module........................................................ 119 reset system.............................................................. 97 rtcc ........................................................................ 219 spi module ............................................................... 191 timer1....................................................................... 177 timer2/3/4/5 (16-bit) ................................................. 181 typical multiplexed port structure ............................ 167 uart ........................................................................ 205 wdt and power-up timer ........................................ 260 brown-out reset (bor) and on-chip voltage regulator................................ 262 c c compilers mplab c18 .............................................................. 266 charge time measurement unit. see ctmu. clock diagram .................................................................. 110 comparator specifications............................................................ 281 comparator module .......................................................... 237 comparator voltage reference (cvref ............................. 241 configuration bit ............................................................... 251 configuring analog port pins ............................................ 168 cpu architecture overview................................................. 34 coprocessor 0 registers ............................................ 35 core exception types................................................. 36 ejtag debug support ............................................... 36 power management.................................................... 36 cpu module ................................................................. 27, 33 ctmu registers .................................................................. 244 customer change notification service............................. 339 customer notification service .......................................... 339 customer support............................................................. 339 d dc and ac characteristics graphs and tables ................................................... 315 dc characteristics............................................................ 270 i/o pin input specifications ...................................... 275 i/o pin output specifications.................................... 278 idle current (i idle ) .................................................... 273 power-down current (i pd )........................................ 274 program memory...................................................... 280 temperature and voltage specifications.................. 271 development support ....................................................... 265 direct memory access (dma) controller.......................... 129 e electrical characteristics .................................................. 269 ac............................................................................. 282 errata .................................................................................. 15 external clock timer1 timing requirements ................................... 288 timer2, 3, 4, 5 timing requirements ....................... 289 timing requirements ............................................... 283 f flash program memory ...................................................... 93 rtsp operation ......................................................... 93 h high voltage detect (hvd)................................. 98, 262, 279 i i/o ports ........................................................................... 167 parallel i/o (pio) ...................................................... 168 write/read timing.................................................... 168 input change notification ................................................. 168 instruction set................................................................... 263 inter-integrated circuit (i2c .............................................. 199 internal voltage reference specifications........................ 281 internet address ............................................................... 339 interrupt controller............................................................ 101 irg, vector and bit location .................................... 102 m memory maps devices with 128 kb of program memory.................. 39 devices with 256 kb of program memory.................. 40 devices with 512 kb of program memory.................. 41 devices with 64 kb of program memory.................... 38 memory organization ......................................................... 37 layout......................................................................... 37 microchip internet web site.............................................. 339 mplab asm30 assembler, linker, librarian ................... 266 mplab integrated development environment software.. 265 mplab pm3 device programmer .................................... 268 mplab real ice in-circuit emulator system ................ 267 mplink object linker/mplib object librarian ................ 266
pic32mx330/350/370/430/450/470 ds60001185b-page 336 preliminary ? 2012-2013 microchip technology inc. o oscillator configuration..................................................... 109 output compare................................................................ 189 p packaging ......................................................................... 319 details ....................................................................... 321 marking ..................................................................... 319 parallel master port (pmp) ............................................... 211 pic32 family usb interface diagram............................... 146 pinout i/o descriptions (table) ............................................ 18 power-on reset (por) and on-chip voltage regulator ................................ 262 power-saving features..................................................... 247 cpu halted methods ................................................ 247 operation .................................................................. 247 with cpu running..................................................... 247 prefetch cache ................................................................. 119 r reader response ............................................................. 340 real-time clock and calendar (rtcc)............................ 219 register map adc ............................................................................ 52 bus matrix ................................................................... 42 comparator ................................................................. 58 comparator voltage reference .................................. 58 ctmu.......................................................................... 83 device and revision id summary .............................. 61 device configuration word summary......................... 61 dma channel 0-3 ....................................................... 55 dma crc ................................................................... 54 dma global................................................................. 54 flash controller........................................................... 59 i2c1 and i2c2 ............................................................. 48 input capture 1-5 ........................................................ 46 interrupt....................................................................... 43 output compare1-5 .................................................... 47 parallel master port .................................................... 81 peripheral pin select input ......................................... 76 peripheral pin select output....................................... 78 porta........................................................................ 62 portb........................................................................ 63 portc ................................................................. 64, 65 portd ................................................................. 66, 67 porte.................................................................. 68, 69 portf ...................................................... 70, 71, 72, 73 portg ................................................................. 74, 75 prefetch....................................................................... 82 rtcc .......................................................................... 83 spi1 and spi2 ............................................................ 51 system control ........................................................... 60 timer1-5...................................................................... 45 uart1-5 ..................................................................... 49 usb............................................................................. 84 registers [ pin name ]r (peripheral pin select input)................. 175 ad1chs (adc input select) .................................... 235 ad1con1 (a/d control 1) ........................................ 227 ad1con1 (adc control 1) .............................. 227, 231 ad1con2 (adc control 2) ...................................... 233 ad1con3 (adc control 3) ...................................... 234 ad1cssl (adc input scan select) ......................... 236 alrmdate (alarm date value) ............................... 227 alrmdateclr (alrmdate clear)....................... 227 alrmdateset (alrmdate set).......................... 227 alrmtime (alarm time value) ............................... 226 alrmtimeclr (alrmtime clear) ........................ 227 alrmtimeinv (alrmtime invert) ......................... 227 alrmtimeset (alrmtime set)............................ 227 bmxbootsz (boot flash (ifm) size ........................ 92 bmxcon (bus matrix configuration) ......................... 87 bmxdkpba (data ram kernel program ? base address) .................................................... 88 bmxdrmsz (data ram size register)..................... 91 bmxdudba (data ram user data base address)... 89 bmxdupba (data ram user program ? base address) .................................................... 90 bmxpfmsz (program flash (pfm) size).................. 92 bmxpupba (program flash (pfm) user program ? base address) .................................................... 91 cheacc (cache access) ........................................ 121 checon (cache control)........................................ 120 chehit (cache hit statistics).................................. 126 chelru (cache lru) ............................................. 125 chemis (cache miss statistics) .............................. 126 chemsk (cache tag mask)................................... 123 chetag (cache tag)............................................. 122 chew0 (cache word 0) .......................................... 123 chew1 (cache word 1) .......................................... 124 chew2 (cache word 2) .......................................... 124 chew3 (cache word 3) .......................................... 125 cm1con (comparator 1 control) ............................ 238 cmstat (comparator control register).................. 239 cnconx (change notice control for portx) ......... 176 ctmucon (ctmu control) ..................................... 244 cvrcon (comparator voltage reference control) 242 dchxcon (dma channel x control) ....................... 135 dchxcptr (dma channel x cell pointer) .............. 142 dchxcsiz (dma channel x cell-size) .................... 142 dchxdat (dma channel x pattern data) ............... 143 dchxdptr (channel x destination pointer) ........... 141 dchxdsa (dma channel x destination ? start address)................................................... 139 dchxdsiz (dma channel x destination size) ........ 140 dchxecon (dma channel x event control) .......... 136 dchxint (dma channel x interrupt control)........... 137 dchxsptr (dma channel x source pointer) ......... 141 dchxssa (dma channel x source start address) . 139 dchxssiz (dma channel x source size) ............... 140 dcrccon (dma crc control)............................... 132 dcrcdata (dma crc data) ................................. 134 dcrcxor (dma crcxor enable) ....................... 134 devcfg0 (device configuration word 0................. 251 devcfg1 (device configuration word 1................. 253 devcfg2 (device configuration word 2................. 255 devcfg3 (device configuration word 3................. 257 devid (device and revision id) .............................. 259 dmaaddr (dma address) ...................................... 131 dmaaddr (dmr address)...................................... 131 dmacon (dma controller control) ......................... 130 dmastat (dma status) .......................................... 131 i2cxcon (i2c control)............................................. 201 i2cxstat (i2c status) ............................................. 203 icxcon (input capture x control)............................ 186 ifsx (interrupt flag status) ...................................... 106 intcon (interrupt control)....................................... 104 intstat (interrupt status)....................................... 105 ipcx (interrupt priority control) ................................ 107 iptmr interrupt proximity timer) ............................. 105
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 337 pic32mx330/350/370/430/450/470 nvmaddr (flash address) ....................................... 95 nvmcon (programming control) .............................. 94 nvmdata (flash program data)............................... 96 nvmkey (programming unlock)................................ 95 nvmsrcaddr (source data address)..................... 96 ocxcon (output compare x control) ..................... 190 osccon (oscillator control) ................................... 111 pfabt (prefetch cache a bort statistics) ................. 127 pmaddr (parallel port address) ............................. 216 pmaen (parallel port pin enable)............................ 217 pmcon (parallel port control) ................................. 212 pmmode (parallel port mode)................................. 214 pmstat (parallel port status (slave modes only).. 218 refocon (reference osci llator control) ............... 115 refotrim (reference oscillator trim) ................... 117 rpnr (peripheral pin select output)........................ 175 rswrst (software reset) ........................................ 99 rtccon (rtc control) ........................................... 220 rtcdate (rtc date value) ................................... 225 rtctime (rtc time value) .................................... 224 spixcon (spi control)............................................. 192 spixcon2 (spi control 2)........................................ 195 spixstat (spi status)............................................. 196 t1con (type a timer control) ................................ 178 txcon (type b timer control) ................................ 183 u1addr (usb address) .......................................... 160 u1bdtp1 (usb bdt page 1) .................................. 162 u1bdtp2 (usb bdt page 2) .................................. 163 u1bdtp3 (usb bdt page 3) .................................. 163 u1cnfg1 (usb configuration 1) ............................. 164 u1con (usb control) .............................................. 158 u1eie (usb error interrupt enable) ......................... 156 u1eir (usb error interrupt status) .......................... 154 u1ep0-u1ep15 (usb endpoint control) ................. 165 u1frmh (usb frame number high)....................... 161 u1frml (usb frame number low) ........................ 160 u1ie (usb interrupt enable)..................................... 153 u1ir (usb interrupt)................................................. 152 u1otgcon (usb otg control) ............................. 150 u1otgie (usb otg interrupt enable) .................... 148 u1otgir (usb otg interrupt status)..................... 147 u1otgstat (usb otg status).............................. 149 u1pwrc (usb power control)................................ 151 u1sof (usb sof threshold).................................. 162 u1stat (usb status) .............................................. 157 u1tok (usb token) ................................................ 161 wdtcon (watchdog timer control) ....................... 261 resets ................................................................................. 97 revision history ................................................................ 333 rtcalrm (rtc alarm control) .................................... 222 s serial peripheral interface (spi) ....................................... 191 software simulator (mplab sim)..................................... 267 special features ............................................................... 251 t timer1 module.................................................................. 177 timer2/3, timer4/5 modules............................................. 181 timing diagrams 10-bit analog-to-digital conversion ? (asam = 0, ssrc<2:0> = 000)........................ 306 10-bit analog-to-digital conversion (asam = 1, ? ssrc<2:0> = 111, samc<4:0> = 00001) ....... 307 ejtag ...................................................................... 313 external clock .......................................................... 282 i/o characteristics .................................................... 285 i2cx bus data (master mode) .................................. 296 i2cx bus data (slave mode) .................................... 299 i2cx bus start/stop bits (master mode)................... 296 i2cx bus start/stop bits (slave mode)..................... 299 input capture (capx) ............................................... 289 ocx/pwm................................................................. 290 output compare (ocx) ............................................ 290 parallel master port read ........................................ 309 parallel master port write......................................... 310 parallel slave port .................................................... 308 spix master mode (cke = 0) ................................... 291 spix master mode (cke = 1) ................................... 292 spix slave mode (cke = 0) ..................................... 293 spix slave mode (cke = 1) ..................................... 294 timer1, 2, 3, 4, 5 external clock .............................. 288 uart reception....................................................... 210 uart transmission (8-bit or 9-bit data) .................. 210 timing requirements clko and i/o ........................................................... 285 timing specifications i2cx bus data requirements (master mode)........... 297 i2cx bus data requirements (slave mode)............. 300 input capture requirements .................................... 289 output compare requirements................................ 290 simple ocx/pwm mode requirements ................... 290 spix master mode (cke = 0) requirements............ 291 spix master mode (cke = 1) requirements............ 292 spix slave mode (cke = 1) requirements.............. 294 spix slave mode requirements (cke = 0).............. 293 u uart ................................................................................ 205 usb on-the-go (otg) .................................................... 145 v v cap pin............................................................................ 262 voltage regulator (on-chip) ............................................ 262 w watchdog timer (wdt).................................................... 260 www address ................................................................. 339 www, on-line support ..................................................... 15
pic32mx330/350/370/430/450/470 ds60001185b-page 338 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 339 pic32mx330/350/370/430/450/470 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faqs), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sale s offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
pic32mx330/350/370/430/450/470 ds60001185b-page 340 preliminary ? 2012-2013 microchip technology inc. reader response it is our intention to provide you with the best document ation possible to ensure succe ssful use of your microchip product. if you wish to provide your comments on organiz ation, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outli ne to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds60001185b pic32mx330/350/ 370/430/450/470 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 341 pic32mx330/350/370/430/450/470 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . architecture mx = 32-bit risc mcu core product groups 3xx = general purpose microcontroller family 4xx = general purpose microcontroller family flash memory family f = flash program memory program memory size 064 = 6 4kb 128 = 128kb 256 = 256kb 512 = 512kb pin count h = 64-pin l = 100-pin speed 80 = 80 mhz temperature range i = -40c to +85c (industrial) v = -40c to +105c (v-temp) package pt = 64-lead (10x10x1 mm) tqfp (thin quad flatpack) pt = 100-lead (12x12x1 mm) tqfp (thin quad flatpack) pf = 100-lead (14x14x1 mm) tqfp (thin quad flatpack) mr = 64-lead (9x9x0.9 mm) qfn (plastic quad flat) tl = 124-lead (9x9x0.9 mm) vtla (very thin leadless array) pattern three-digit qtp, sqtp, code or special requirements (blank otherwise) es = engineering sample example: pic32mx330f064h-80i/pt: ? general purpose pic32, ? 32-bit risc mcu, ? 64 kb program memory, ? 64-pin, industrial temperature, ? tqfp package. microchip brand architecture flash memory family pin count product groups program memory size (kb) pic32 mx 3xx f 064 h t - 80 i / pt - xxx flash memory family speed pattern package temperature range tape and reel flag (if applicable)
pic32mx330/350/370/430/450/470 ds60001185b-page 342 preliminary ? 2012-2013 microchip technology inc. notes:
? 2012-2013 microchip technology inc. preliminary ds60001185b-page 343 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no re presentations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, th e microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademar ks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, a pplication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62077-154-9 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
ds60001185b-page 344 preliminary ? 2012-2013 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - hangzhou tel: 86-571-2819-3187 fax: 86-571-2819-3189 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 fax: 886-7-330-9305 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 worldwide sales and service 11/29/12

▲Up To Search▲

Price & Availability of PIC32MX470F512H

	To Download PIC32MX470F512H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .